From: Stafford Horne <shorne@gmail.com>
To: openrisc@lists.librecores.org
Subject: [OpenRISC] [PATCH v3 2/5] or1k: Fix issues with msoft-div
Date: Tue, 9 Jul 2019 22:06:23 +0900 [thread overview]
Message-ID: <20190709130626.11226-3-shorne@gmail.com> (raw)
In-Reply-To: <20190709130626.11226-1-shorne@gmail.com>
Fixes bad assembly logic with software divide as reported by Richard Selvaggi.
Also, add a basic test to verify the soft math works when enabled.
gcc/testsuite/ChangeLog:
PR target/90362
* gcc.target/or1k/div-mul-3.c: New test.
libgcc/ChangeLog:
PR target/90362
* config/or1k/lib1funcs.S (__udivsi3): Change l.sfeqi
to l.sfeq and l.sfltsi to l.sflts equivalents as the immediate
instructions are not available on every processor. Change a
l.bnf to l.bf to fix logic issue.
---
gcc/testsuite/gcc.target/or1k/div-mul-3.c | 31 +++++++++++++++++++++++
libgcc/config/or1k/lib1funcs.S | 6 ++---
2 files changed, 34 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/or1k/div-mul-3.c
diff --git a/gcc/testsuite/gcc.target/or1k/div-mul-3.c b/gcc/testsuite/gcc.target/or1k/div-mul-3.c
new file mode 100644
index 00000000000..2c4f91b7e98
--- /dev/null
+++ b/gcc/testsuite/gcc.target/or1k/div-mul-3.c
@@ -0,0 +1,31 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -msoft-div -msoft-mul" } */
+
+struct testcase {
+ int a;
+ int b;
+ int c;
+ int expected;
+};
+
+struct testcase tests[] = {
+ {2, 200, 3, 133},
+ {3, 300, 3, 300},
+ {2, 500, 3, 333},
+ {4, 250, 3, 333},
+ {0, 0, 0, 0}
+};
+
+int calc (int a, int b, int c) {
+ return a * b / c;
+}
+
+int main () {
+ int fail = 0;
+ struct testcase *tc;
+
+ for (int i = 0; (tc = &tests[i], tc->c); i++)
+ fail |= (calc (tc->a, tc->b, tc->c) != tc->expected);
+
+ return fail;
+}
diff --git a/libgcc/config/or1k/lib1funcs.S b/libgcc/config/or1k/lib1funcs.S
index d2103923486..6d058977229 100644
--- a/libgcc/config/or1k/lib1funcs.S
+++ b/libgcc/config/or1k/lib1funcs.S
@@ -68,18 +68,18 @@ __udivmodsi3_internal:
is not clobbered by this routine, and use that as to
save a return address without creating a stack frame. */
- l.sfeqi r4, 0 /* division by zero; return 0. */
+ l.sfeq r4, r0 /* division by zero; return 0. */
l.ori r11, r0, 0 /* initial quotient */
l.bf 9f
l.ori r12, r3, 0 /* initial remainder */
/* Given X/Y, shift Y left until Y >= X. */
l.ori r6, r0, 1 /* mask = 1 */
-1: l.sfltsi r4, 0 /* y has msb set */
+1: l.sflts r4, r0 /* y has msb set */
l.bf 2f
l.sfltu r4, r12 /* y < x */
l.add r4, r4, r4 /* y <<= 1 */
- l.bnf 1b
+ l.bf 1b
l.add r6, r6, r6 /* mask <<= 1 */
/* Shift Y back to the right again, subtracting from X. */
--
2.21.0
next prev parent reply other threads:[~2019-07-09 13:06 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-09 13:06 [OpenRISC] [PATCH v3 0/5] OpenRISC updates for 10 (fpu, fixes) Stafford Horne
2019-07-09 13:06 ` [OpenRISC] [PATCH v3 1/5] or1k: Fix code quality for volatile memory loads Stafford Horne
2019-07-09 13:06 ` Stafford Horne [this message]
2019-07-09 13:06 ` [OpenRISC] [PATCH v3 3/5] or1k: Add mrori option, fix option docs Stafford Horne
2019-07-09 13:06 ` [OpenRISC] [PATCH v3 4/5] or1k: Initial support for FPU Stafford Horne
2019-07-09 13:06 ` [OpenRISC] [PATCH v3 5/5] or1k: only force reg for immediates Stafford Horne
2019-07-16 21:09 ` [OpenRISC] [PATCH v3 0/5] OpenRISC updates for 10 (fpu, fixes) Stafford Horne
2019-07-23 20:30 ` Stafford Horne
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