From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Subject: Re: DW-DMA: Probe failures on broadwell Date: Wed, 10 Jul 2019 19:43:46 +0300 Message-ID: <20190710164346.GP9224@smile.fi.intel.com> References: <20190709131401.GA9224@smile.fi.intel.com> <20190709132943.GB9224@smile.fi.intel.com> <20190709133448.GC9224@smile.fi.intel.com> <20190709133847.GD9224@smile.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 612E1F800DE for ; Wed, 10 Jul 2019 18:43:52 +0200 (CEST) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" To: Curtis Malainey Cc: ALSA development , Ross Zwisler , Fletcher Woodruff , Liam Girdwood , dmaengine@vger.kernel.org, Pierre-louis Bossart List-Id: alsa-devel@alsa-project.org On Tue, Jul 09, 2019 at 12:27:49PM -0700, Curtis Malainey wrote: > Hi Andy, Please, don't top post in the public mailing lists, community doesn't like it. > Thanks for the information, we are running a 4.14 kernel so we don't > have the idma32 driver, I will see if I can backport it and report > back if the fix works. Driver is supporting iDMA 32-bit in v4.14 AFAICS. The missed stuff is a split and some fixes here and there. Here is the list of patches I have in a range v4.14..v5.2 (I deliberately dropped the insignificant ones) 934891b0a16c dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit 91f0ff883e9a dmaengine: dw: Reset DRAIN bit when resume the channel 69da8be90d5e dmaengine: dw: Split DW and iDMA 32-bit operations 87fe9ae84d7b dmaengine: dw: Add missed multi-block support for iDMA 32-bit ffe843b18211 dmaengine: dw: Fix FIFO size for Intel Merrifield 7b0c03ecc42f dmaengine: dw-dmac: implement dma protection control setting For me sounds like fairly easy to backport. > On Tue, Jul 9, 2019 at 6:38 AM Andy Shevchenko > wrote: > > > > On Tue, Jul 09, 2019 at 04:34:48PM +0300, Andy Shevchenko wrote: > > > On Tue, Jul 09, 2019 at 04:29:43PM +0300, Andy Shevchenko wrote: > > > > On Tue, Jul 09, 2019 at 04:14:01PM +0300, Andy Shevchenko wrote: > > > > > On Mon, Jul 08, 2019 at 01:50:07PM -0700, Curtis Malainey wrote: > > > > > > > > > So, the correct fix is to provide a platform data, like it's done in > > > > > drivers/dma/dw/pci.c::idma32_pdata, in the sst-firmware.c::dw_probe(), and call > > > > > idma32_dma_probe() with idma32_dma_remove() respectively on removal stage. > > > > > > > > > > (It will require latest patches to be applied, which are material for v5.x) > > > > > > > > Below completely untested patch to try > > > > > > Also, it might require to set proper request lines (currently it uses 0 AFAICS). > > > Something like it's done in drivers/spi/spi-pxa2xx-pci.c for Intel Merrifield. > > > > And SST_DSP_DMA_MAX_BURST seems encoded while it's should be simple number, > > like 8 (bytes). Also SPI PXA is an example to look into. > > > > I doubt it has been validated with upstream driver (I know about some internal > > drivers, hacked version of dw one, you may find sources somewhere in public). -- With Best Regards, Andy Shevchenko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FC80C74A21 for ; Wed, 10 Jul 2019 16:43:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3D5A320665 for ; Wed, 10 Jul 2019 16:43:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727230AbfGJQnu (ORCPT ); Wed, 10 Jul 2019 12:43:50 -0400 Received: from mga03.intel.com ([134.134.136.65]:24221 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726957AbfGJQnu (ORCPT ); Wed, 10 Jul 2019 12:43:50 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jul 2019 09:43:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,475,1557212400"; d="scan'208";a="249523913" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.145]) by orsmga001.jf.intel.com with ESMTP; 10 Jul 2019 09:43:47 -0700 Received: from andy by smile with local (Exim 4.92) (envelope-from ) id 1hlFh4-00061t-7A; Wed, 10 Jul 2019 19:43:46 +0300 Date: Wed, 10 Jul 2019 19:43:46 +0300 From: Andy Shevchenko To: Curtis Malainey Cc: Ross Zwisler , Fletcher Woodruff , dmaengine@vger.kernel.org, ALSA development , Pierre-louis Bossart , Liam Girdwood Subject: Re: DW-DMA: Probe failures on broadwell Message-ID: <20190710164346.GP9224@smile.fi.intel.com> References: <20190709131401.GA9224@smile.fi.intel.com> <20190709132943.GB9224@smile.fi.intel.com> <20190709133448.GC9224@smile.fi.intel.com> <20190709133847.GD9224@smile.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo User-Agent: Mutt/1.10.1 (2018-07-13) Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On Tue, Jul 09, 2019 at 12:27:49PM -0700, Curtis Malainey wrote: > Hi Andy, Please, don't top post in the public mailing lists, community doesn't like it. > Thanks for the information, we are running a 4.14 kernel so we don't > have the idma32 driver, I will see if I can backport it and report > back if the fix works. Driver is supporting iDMA 32-bit in v4.14 AFAICS. The missed stuff is a split and some fixes here and there. Here is the list of patches I have in a range v4.14..v5.2 (I deliberately dropped the insignificant ones) 934891b0a16c dmaengine: dw: Don't pollute CTL_LO on iDMA 32-bit 91f0ff883e9a dmaengine: dw: Reset DRAIN bit when resume the channel 69da8be90d5e dmaengine: dw: Split DW and iDMA 32-bit operations 87fe9ae84d7b dmaengine: dw: Add missed multi-block support for iDMA 32-bit ffe843b18211 dmaengine: dw: Fix FIFO size for Intel Merrifield 7b0c03ecc42f dmaengine: dw-dmac: implement dma protection control setting For me sounds like fairly easy to backport. > On Tue, Jul 9, 2019 at 6:38 AM Andy Shevchenko > wrote: > > > > On Tue, Jul 09, 2019 at 04:34:48PM +0300, Andy Shevchenko wrote: > > > On Tue, Jul 09, 2019 at 04:29:43PM +0300, Andy Shevchenko wrote: > > > > On Tue, Jul 09, 2019 at 04:14:01PM +0300, Andy Shevchenko wrote: > > > > > On Mon, Jul 08, 2019 at 01:50:07PM -0700, Curtis Malainey wrote: > > > > > > > > > So, the correct fix is to provide a platform data, like it's done in > > > > > drivers/dma/dw/pci.c::idma32_pdata, in the sst-firmware.c::dw_probe(), and call > > > > > idma32_dma_probe() with idma32_dma_remove() respectively on removal stage. > > > > > > > > > > (It will require latest patches to be applied, which are material for v5.x) > > > > > > > > Below completely untested patch to try > > > > > > Also, it might require to set proper request lines (currently it uses 0 AFAICS). > > > Something like it's done in drivers/spi/spi-pxa2xx-pci.c for Intel Merrifield. > > > > And SST_DSP_DMA_MAX_BURST seems encoded while it's should be simple number, > > like 8 (bytes). Also SPI PXA is an example to look into. > > > > I doubt it has been validated with upstream driver (I know about some internal > > drivers, hacked version of dw one, you may find sources somewhere in public). -- With Best Regards, Andy Shevchenko