Re: [kvm-unit-tests PATCH] tscdeadline_latency: Check condition first before loop

[Sean Christopherson <sean.j.christopherson@intel.com>]

On Fri, Jul 12, 2019 at 07:27:36AM +0800, Peter Xu wrote:
> On Thu, Jul 11, 2019 at 07:05:53AM -0700, Sean Christopherson wrote:
> > Ensuring the first hlt lands in an interrupt shadow should prevent getting
> > into a halted state after the timer has been disabled, e.g.:
> > 
> >     irq_disable();
> >     test_tsc_deadline_timer();
> > 
> >     do {
> >         safe_halt();
> >     } while (!hitmax && table_idx < size);
> 
> Yes seems better, thanks for the suggestion (though I'll probably also
> need to remove the hidden sti in start_tsc_deadline_timer).
> 
> Is safe_halt() really safe?  I mean, IRQ handler could still run
> before HLT right after STI right?  Though no matter what I think it's
> fine for this test case because we'll skip the first IRQ after all.
> Just curious.

It's safe, at least on modern hardware.  Everything since P6, and I
think all AMD CPUs?, have an interrupt shadow where interrupts are
blocked for one additional instruction after being enabled by STI.