[PATCH v2 00/10] DC3CO Support for TGL.

From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH v2 00/10] DC3CO Support for TGL.
Date: Wed, 17 Jul 2019 15:57:55 +0530	[thread overview]
Message-ID: <20190717102804.27202-1-anshuman.gupta@intel.com> (raw)

This update is a rebased and has addressed few review comment provided by
Imre on IRC.

DMC f/w DC3CO entry/exit sequence can be found at DC3CO HAS.

I am able to validate that DC3CO counter increments on pipe2d emulator.
DC5 counter also increment after DC3CO disallow. 
I will test it on real H/W once it shipped to BA, 
till then we can finish with review and freeze its design.

One patch of this series  "0007-drm-i915-tgl-DC3CO-PSR2-helper.patch"
will require rebase after https://patchwork.freedesktop.org/series/62416/
series will merged to drm-tip. 
TGL supports DC3CO only on PipeA in LPSP mpde, 
so DC3CO doesn't depends on TGL PSR feature on Transcoder B.

DC3CO requirements:
*Audio codec idle and disabled.
*External displays disabled. WD transcoders and DP/HDMI transcoders must be disabled.
*Backlight cannot be driven from the display utility pin. It can be driven from the south display.
*This feature should be enabled only in Display Video playback on eDP.
*DC5 and DC6 not allowed when this feature is enabled.
*PSR2 deep sleep disabled (PSR2_CTL Idle Frames = 0000b)
*Disable DC3co before mode set, or other Aux, PLL, and DBUF programming,
 and do not re-enable until after that programming is completed.
*DC3co must not be enabled until after PSR2 is enabled.
*DC3co must be disabled before PSR2 is disabled.

B.Specs:49196

Anshuman Gupta (10):
  drm/i915/tgl:Added DC3CO required register and bits.
  i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask.
  i915:Added DC3CO power well.
  drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6.
  drm/i915/tgl:Added helper function to prefer dc3co over dc5.
  drm/i915/tgl:Added VIDEO power domain.
  drm/i915/tgl:DC3CO PSR2 helper.
  drm/i915/tgl:switch between dc3co and dc5 based on display idleness.
  drm/i915/tgl:Added DC3CO counter in i915_dmc_info.
  drm/i915/tgl:Added new DC5/DC6 counter.

 drivers/gpu/drm/i915/display/intel_display.c  |  39 +++
 .../drm/i915/display/intel_display_power.c    | 226 +++++++++++++++++-
 .../drm/i915/display/intel_display_power.h    |  10 +
 drivers/gpu/drm/i915/display/intel_psr.c      |  44 ++++
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +
 drivers/gpu/drm/i915/i915_debugfs.c           |  17 +-
 drivers/gpu/drm/i915/i915_drv.h               |   8 +
 drivers/gpu/drm/i915/i915_params.c            |   3 +-
 drivers/gpu/drm/i915/i915_reg.h               |  13 +
 drivers/gpu/drm/i915/intel_pm.c               |   2 +-
 drivers/gpu/drm/i915/intel_pm.h               |   2 +
 11 files changed, 357 insertions(+), 9 deletions(-)

-- 
2.21.0

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