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From: Anshuman Gupta <anshuman.gupta@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [PATCH v2 10/10] drm/i915/tgl:Added new DC5/DC6 counter.
Date: Wed, 17 Jul 2019 19:39:49 +0530	[thread overview]
Message-ID: <20190717140949.29329-11-anshuman.gupta@intel.com> (raw)
In-Reply-To: <20190717140949.29329-1-anshuman.gupta@intel.com>

TGL onwards we have new DC5 and DC6 counter
DMC_DEBUG1 and DMC_DEBUG2, these counter will retain
there values upon DMC reset.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 8 +++++---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b382b0b9e430..fa09d93c639a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2515,11 +2515,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
 
 	seq_printf(m, "DC3 -> DC5 count: %d\n",
-		   I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
-						    SKL_CSR_DC3_DC5_COUNT));
+		   I915_READ(IS_TIGERLAKE(dev_priv) ? DMC_DEBUG1 :
+			     (IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
+						    SKL_CSR_DC3_DC5_COUNT)));
 	if (!IS_GEN9_LP(dev_priv))
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
-			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
+			   I915_READ(IS_TIGERLAKE(dev_priv) ? DMC_DEBUG2 :
+				     SKL_CSR_DC5_DC6_COUNT));
 
 out:
 	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 68e4b78e4a64..5e567bd4f820 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7266,6 +7266,8 @@ enum {
 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
 
 /* DMC DEBUG COUNTERS for TGL*/
+#define DMC_DEBUG1		_MMIO(0x101084)
+#define DMC_DEBUG2		_MMIO(0x101088)
 #define DMC_DEBUG3		_MMIO(0x101090) /*DC3CO debug counter*/
 
 /* interrupts */
-- 
2.21.0

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  parent reply	other threads:[~2019-07-17 14:14 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-17 14:09 [PATCH v2 00/10] DC3CO Support for TGL Anshuman Gupta
2019-07-17 14:09 ` [PATCH v2 01/10] drm/i915/tgl:Added DC3CO required register and bits Anshuman Gupta
2019-07-17 14:09 ` [PATCH v2 02/10] i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask Anshuman Gupta
2019-07-17 14:09 ` [PATCH v2 03/10] i915:Added DC3CO power well Anshuman Gupta
2019-07-17 14:09 ` [PATCH v2 04/10] drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6 Anshuman Gupta
2019-07-17 14:09 ` [PATCH v2 05/10] drm/i915/tgl:Added helper function to prefer dc3co over dc5 Anshuman Gupta
2019-07-17 14:09 ` [PATCH v2 06/10] drm/i915/tgl:Added VIDEO power domain Anshuman Gupta
2019-07-17 14:09 ` [PATCH v2 07/10] drm/i915/tgl:DC3CO PSR2 helper Anshuman Gupta
2019-07-17 14:09 ` [PATCH v2 08/10] drm/i915/tgl:switch between dc3co and dc5 based on display idleness Anshuman Gupta
2019-07-17 14:09 ` [PATCH v2 09/10] drm/i915/tgl:Added DC3CO counter in i915_dmc_info Anshuman Gupta
2019-07-17 14:09 ` Anshuman Gupta [this message]
2019-07-17 14:29 ` ✗ Fi.CI.BAT: failure for DC3CO Support for TGL Patchwork

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