[PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On VLV/CHV there is some kind of linkage between the cdclk frequency
and the DP link frequency. The spec says:
"For DP audio configuration, cdclk frequency shall be set to
 meet the following requirements:
 DP Link Frequency(MHz) | Cdclk frequency(MHz)
 270                    | 320 or higher
 162                    | 200 or higher"

I suspect that would more accurately be expressed as
"cdclk >= DP link clock", and in any case we can express it like
that in the code because of the limited set of cdclk and link
frequencies we support.

Without this we can end up in a situation where the cdclk
is too low and enabling DP audio will kill the pipe. Happens
eg. with 2560x1440 modes where the 266MHz cdclk is sufficient
to pump the pixels (241.5 MHz dotclock) but is too low for
the DP audio due to the link frequency being 270 MHz.

Cc: stable@vger.kernel.org
Tested-by: Stefan Gottwald <gottwald@igel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111149
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index d0581a1ac243..93b0d190c184 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2262,6 +2262,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
 		min_cdclk = max(2 * 96000, min_cdclk);
 
+	/*
+	 * "For DP audio configuration, cdclk frequency shall be set to
+	 *  meet the following requirements:
+	 *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
+	 *  270                    | 320 or higher
+	 *  162                    | 200 or higher"
+	 */
+	if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
+	    intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
+		min_cdclk = max(crtc_state->port_clock, min_cdclk);
+
 	/*
 	 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
 	 * than 320000KHz.
-- 
2.21.0

✗ Fi.CI.SPARSE: warning for drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[Patchwork]

== Series Details ==

Series: drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV
URL   : https://patchwork.freedesktop.org/series/63808/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV
-O:drivers/gpu/drm/i915/display/intel_cdclk.c:2263:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2263:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2274:29: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/display/intel_cdclk.c:2274:29: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[Patchwork]

== Series Details ==

Series: drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV
URL   : https://patchwork.freedesktop.org/series/63808/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6498 -> Patchwork_13671
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/

Known issues
------------

  Here are the changes found in Patchwork_13671 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-kbl-7500u:       [PASS][1] -> [DMESG-WARN][2] ([fdo#105128] / [fdo#107139])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/fi-kbl-7500u/igt@gem_exec_suspend@basic-s4-devices.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/fi-kbl-7500u/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live_execlists:
    - fi-bwr-2160:        [PASS][3] -> [DMESG-WARN][4] ([fdo#111115])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/fi-bwr-2160/igt@i915_selftest@live_execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/fi-bwr-2160/igt@i915_selftest@live_execlists.html

  * igt@i915_selftest@live_hangcheck:
    - fi-bwr-2160:        [PASS][5] -> [DMESG-FAIL][6] ([fdo#111115])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/fi-bwr-2160/igt@i915_selftest@live_hangcheck.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-cml-u2:          [PASS][7] -> [FAIL][8] ([fdo#109483])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html

  
#### Possible fixes ####

  * igt@gem_ctx_create@basic-files:
    - fi-icl-u3:          [INCOMPLETE][9] ([fdo#107713] / [fdo#109100]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/fi-icl-u3/igt@gem_ctx_create@basic-files.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/fi-icl-u3/igt@gem_ctx_create@basic-files.html

  * igt@i915_selftest@live_execlists:
    - fi-skl-gvtdvm:      [DMESG-FAIL][11] ([fdo#111108]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/fi-skl-gvtdvm/igt@i915_selftest@live_execlists.html

  
  [fdo#105128]: https://bugs.freedesktop.org/show_bug.cgi?id=105128
  [fdo#107139]: https://bugs.freedesktop.org/show_bug.cgi?id=107139
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108
  [fdo#111115]: https://bugs.freedesktop.org/show_bug.cgi?id=111115


Participating hosts (55 -> 47)
------------------------------

  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6498 -> Patchwork_13671

  CI_DRM_6498: d8b53b0eabbd01f4efc091e9cadc5cde41a6362a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5100: 0ea68a1efbfcc4961f2f816ab59e4ad8136c6250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13671: 190081b96e86ee9c071131622108e5d860c94949 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

190081b96e86 drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/
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Re: [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[Sasha Levin]

Hi,

[This is an automated email]

This commit has been processed because it contains a -stable tag.
The stable tag indicates that it's relevant for the following trees: all

The bot has tested the following trees: v5.2.1, v5.1.18, v4.19.59, v4.14.133, v4.9.185, v4.4.185.

v5.2.1: Failed to apply! Possible dependencies:
    Unable to calculate

v5.1.18: Failed to apply! Possible dependencies:
    Unable to calculate

v4.19.59: Failed to apply! Possible dependencies:
    Unable to calculate

v4.14.133: Failed to apply! Possible dependencies:
    9c61de4c69a2 ("drm/i915: Consolidate max_cdclk_freq check in intel_crtc_compute_min_cdclk()")
    c8dae55a8ced ("drm/i915/vlv: Add cdclk workaround for DSI")
    d305e0614601 ("drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock"")

v4.9.185: Failed to apply! Possible dependencies:
    294591cfbd2b ("drm/i915: Update kerneldoc for intel_dpll_mgr.c")
    2c42e5351445 ("drm/i915: Rename intel_shared_dpll_config to intel_shared_dpll_state")
    3c0fb58820ac ("drm/i915: Rename intel_shared_dpll_commit() to _swap_state()")
    47a6bc61b866 ("drm/i915: Move broxton phy code to intel_dpio_phy.c")
    7ff89ca21358 ("drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c")
    842d416654eb ("drm/i915: Create a struct to hold information about the broxton phys")
    8cbeb06dc6b5 ("drm/i915: Implement cdclk restrictions based on Azalia BCLK")
    a1c414ee82d9 ("drm/i915: Introduce intel_release_shared_dpll()")
    b284eedaf74b ("drm/i915: Pass lane count to bxt_ddi_phy_calc_lane_optmin_mask()")
    b6e08203cc1f ("drm/i915: Move broxton vswing sequence to intel_dpio_phy.c")
    c8dae55a8ced ("drm/i915/vlv: Add cdclk workaround for DSI")
    ed37892e6df2 ("drm/i915: Address broxton phy registers based on phy and channel number")
    f38861b814b5 ("drm/i915: Move DPIO phy documentation section to intel_dpio_phy.c")

v4.4.185: Failed to apply! Possible dependencies:
    12fda3876d08 ("drm/i915/ibx: Ensure the HW is powered during PLL HW readout")
    22cba31bae9d ("Documentation/sphinx: add basic working Sphinx configuration and build")
    294591cfbd2b ("drm/i915: Update kerneldoc for intel_dpll_mgr.c")
    64e1077a1f93 ("drm/i915: Clean up eDP PLL state asserts")
    7abd4b35a577 ("drm/i915: Move shared dpll code to a new file")
    7ff89ca21358 ("drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c")
    87ad321287ae ("drm/i915: add onoff utility function")
    8cbeb06dc6b5 ("drm/i915: Implement cdclk restrictions based on Azalia BCLK")
    c8dae55a8ced ("drm/i915/vlv: Add cdclk workaround for DSI")
    ca00c2b986ea ("Documentation/gpu: split up the gpu documentation")
    cb597fcea5c2 ("Documentation/gpu: add new gpu.rst converted from DocBook gpu.tmpl")
    f169660ed4e5 ("drm/i915/dp: Add a standalone function to obtain shared dpll for HSW/BDW/SKL/BXT")


NOTE: The patch will not be queued to stable trees until it is upstream.

How should we proceed with this patch?

--
Thanks,
Sasha
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✓ Fi.CI.IGT: success for drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[Patchwork]

== Series Details ==

Series: drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV
URL   : https://patchwork.freedesktop.org/series/63808/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6498_full -> Patchwork_13671_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13671_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2] ([fdo#104108])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-skl4/igt@gem_softpin@noreloc-s3.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-skl7/igt@gem_softpin@noreloc-s3.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-apl:          [PASS][3] -> [DMESG-WARN][4] ([fdo#108686])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-apl8/igt@gem_tiled_swapping@non-threaded.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-apl1/igt@gem_tiled_swapping@non-threaded.html
    - shard-glk:          [PASS][5] -> [DMESG-WARN][6] ([fdo#108686])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-glk7/igt@gem_tiled_swapping@non-threaded.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-glk3/igt@gem_tiled_swapping@non-threaded.html
    - shard-kbl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#108686])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-kbl1/igt@gem_tiled_swapping@non-threaded.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-kbl6/igt@gem_tiled_swapping@non-threaded.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-kbl:          [PASS][9] -> [SKIP][10] ([fdo#109271])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-kbl4/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-kbl2/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_suspend@sysfs-reader:
    - shard-apl:          [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +4 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-apl7/igt@i915_suspend@sysfs-reader.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-apl1/igt@i915_suspend@sysfs-reader.html

  * igt@kms_flip@dpms-vs-vblank-race:
    - shard-glk:          [PASS][13] -> [FAIL][14] ([fdo#103060])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-glk8/igt@kms_flip@dpms-vs-vblank-race.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-glk3/igt@kms_flip@dpms-vs-vblank-race.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([fdo#103167]) +3 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-pgflip-blt.html

  * igt@kms_psr@psr2_cursor_blt:
    - shard-iclb:         [PASS][17] -> [SKIP][18] ([fdo#109441]) +3 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-iclb8/igt@kms_psr@psr2_cursor_blt.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][19] -> [FAIL][20] ([fdo#99912])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-apl4/igt@kms_setmode@basic.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-apl7/igt@kms_setmode@basic.html

  * igt@perf@blocking:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([fdo#110728])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-skl2/igt@perf@blocking.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-skl5/igt@perf@blocking.html

  
#### Possible fixes ####

  * igt@gem_exec_schedule@smoketest-render:
    - shard-iclb:         [INCOMPLETE][23] ([fdo#107713]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-iclb7/igt@gem_exec_schedule@smoketest-render.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-iclb4/igt@gem_exec_schedule@smoketest-render.html

  * igt@i915_selftest@live_hangcheck:
    - shard-iclb:         [INCOMPLETE][25] ([fdo#107713] / [fdo#108569]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-iclb4/igt@i915_selftest@live_hangcheck.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-iclb6/igt@i915_selftest@live_hangcheck.html

  * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic:
    - shard-hsw:          [FAIL][27] ([fdo#105767]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-hsw5/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-atomic.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          [INCOMPLETE][29] ([fdo#109507]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-skl10/igt@kms_flip@flip-vs-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-skl2/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [DMESG-WARN][31] ([fdo#108566]) -> [PASS][32] +4 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-apl4/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-iclb:         [FAIL][33] ([fdo#103167]) -> [PASS][34] +4 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-apl:          [FAIL][35] ([fdo#103167]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-apl3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-apl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html
    - shard-skl:          [FAIL][37] ([fdo#103167]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-skl8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-skl7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [DMESG-WARN][39] ([fdo#108566]) -> [PASS][40] +2 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [FAIL][41] ([fdo#108145]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-skl5/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [FAIL][43] ([fdo#103166]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-iclb1/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-iclb8/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_cursor_mmap_cpu:
    - shard-iclb:         [SKIP][45] ([fdo#109441]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6498/shard-iclb4/igt@kms_psr@psr2_cursor_mmap_cpu.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html

  
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * Linux: CI_DRM_6498 -> Patchwork_13671

  CI_DRM_6498: d8b53b0eabbd01f4efc091e9cadc5cde41a6362a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5100: 0ea68a1efbfcc4961f2f816ab59e4ad8136c6250 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13671: 190081b96e86ee9c071131622108e5d860c94949 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13671/
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Re: [Intel-gfx] [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[Chris Wilson]

Quoting Ville Syrjala (2019-07-17 12:45:36)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On VLV/CHV there is some kind of linkage between the cdclk frequency
> and the DP link frequency. The spec says:
> "For DP audio configuration, cdclk frequency shall be set to
>  meet the following requirements:
>  DP Link Frequency(MHz) | Cdclk frequency(MHz)
>  270                    | 320 or higher
>  162                    | 200 or higher"
> 
> I suspect that would more accurately be expressed as
> "cdclk >= DP link clock", and in any case we can express it like
> that in the code because of the limited set of cdclk and link
> frequencies we support.
> 
> Without this we can end up in a situation where the cdclk
> is too low and enabling DP audio will kill the pipe. Happens
> eg. with 2560x1440 modes where the 266MHz cdclk is sufficient
> to pump the pixels (241.5 MHz dotclock) but is too low for
> the DP audio due to the link frequency being 270 MHz.
> 
> Cc: stable@vger.kernel.org
> Tested-by: Stefan Gottwald <gottwald@igel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111149
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d0581a1ac243..93b0d190c184 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2262,6 +2262,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
>         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
>                 min_cdclk = max(2 * 96000, min_cdclk);
>  
> +       /*
> +        * "For DP audio configuration, cdclk frequency shall be set to
> +        *  meet the following requirements:
> +        *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
> +        *  270                    | 320 or higher
> +        *  162                    | 200 or higher"
> +        */
> +       if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> +           intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
> +               min_cdclk = max(crtc_state->port_clock, min_cdclk);

I tracked port_clock down to being the dp link clock (162 or 270) so
that part of the story checks out.

Judging by the rest of the function, I buy that the cdclk and link clock
may be inscrutably tied together, and accept the test result that the
cdclk must be at least the link clock with audio enabled.

It may be that a corner case does require a higher frequency (rather
than just bumping from 266 to 270), but for here and now
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris

Re: [Intel-gfx] [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[Ville Syrjälä]

On Thu, Jul 18, 2019 at 06:11:08PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-07-17 12:45:36)
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > On VLV/CHV there is some kind of linkage between the cdclk frequency
> > and the DP link frequency. The spec says:
> > "For DP audio configuration, cdclk frequency shall be set to
> >  meet the following requirements:
> >  DP Link Frequency(MHz) | Cdclk frequency(MHz)
> >  270                    | 320 or higher
> >  162                    | 200 or higher"
> > 
> > I suspect that would more accurately be expressed as
> > "cdclk >= DP link clock", and in any case we can express it like
> > that in the code because of the limited set of cdclk and link
> > frequencies we support.
> > 
> > Without this we can end up in a situation where the cdclk
> > is too low and enabling DP audio will kill the pipe. Happens
> > eg. with 2560x1440 modes where the 266MHz cdclk is sufficient
> > to pump the pixels (241.5 MHz dotclock) but is too low for
> > the DP audio due to the link frequency being 270 MHz.
> > 
> > Cc: stable@vger.kernel.org
> > Tested-by: Stefan Gottwald <gottwald@igel.com>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111149
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++++++++
> >  1 file changed, 11 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index d0581a1ac243..93b0d190c184 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -2262,6 +2262,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> >         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> >                 min_cdclk = max(2 * 96000, min_cdclk);
> >  
> > +       /*
> > +        * "For DP audio configuration, cdclk frequency shall be set to
> > +        *  meet the following requirements:
> > +        *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
> > +        *  270                    | 320 or higher
> > +        *  162                    | 200 or higher"
> > +        */
> > +       if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> > +           intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
> > +               min_cdclk = max(crtc_state->port_clock, min_cdclk);
> 
> I tracked port_clock down to being the dp link clock (162 or 270) so
> that part of the story checks out.
> 
> Judging by the rest of the function, I buy that the cdclk and link clock
> may be inscrutably tied together, and accept the test result that the
> cdclk must be at least the link clock with audio enabled.
> 
> It may be that a corner case does require a higher frequency (rather
> than just bumping from 266 to 270), but for here and now

Yeah there could be some extra headroom required. But our cdclk
can only be 200, 266, 320 or 400 MHz (and 200 won't actually get used
due to inexplicable display failure when try to use it). So in practice
we going to actually get bumped 162->266 and 270->320 here. I should
have expressed that better in the commit message.

> Acked-by: Chris Wilson <chris@chris-wilson.co.uk>

Thanks. I amended the explanation a bit and pushed to dinq.

-- 
Ville Syrjälä
Intel

Re: [Intel-gfx] [PATCH] drm/i915: Make sure cdclk is high enough for DP audio on VLV/CHV

[Chris Wilson]

Quoting Ville Syrjälä (2019-07-18 19:04:56)
> On Thu, Jul 18, 2019 at 06:11:08PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2019-07-17 12:45:36)
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > On VLV/CHV there is some kind of linkage between the cdclk frequency
> > > and the DP link frequency. The spec says:
> > > "For DP audio configuration, cdclk frequency shall be set to
> > >  meet the following requirements:
> > >  DP Link Frequency(MHz) | Cdclk frequency(MHz)
> > >  270                    | 320 or higher
> > >  162                    | 200 or higher"
> > > 
> > > I suspect that would more accurately be expressed as
> > > "cdclk >= DP link clock", and in any case we can express it like
> > > that in the code because of the limited set of cdclk and link
> > > frequencies we support.
> > > 
> > > Without this we can end up in a situation where the cdclk
> > > is too low and enabling DP audio will kill the pipe. Happens
> > > eg. with 2560x1440 modes where the 266MHz cdclk is sufficient
> > > to pump the pixels (241.5 MHz dotclock) but is too low for
> > > the DP audio due to the link frequency being 270 MHz.
> > > 
> > > Cc: stable@vger.kernel.org
> > > Tested-by: Stefan Gottwald <gottwald@igel.com>
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111149
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++++++++
> > >  1 file changed, 11 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > index d0581a1ac243..93b0d190c184 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > > @@ -2262,6 +2262,17 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
> > >         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
> > >                 min_cdclk = max(2 * 96000, min_cdclk);
> > >  
> > > +       /*
> > > +        * "For DP audio configuration, cdclk frequency shall be set to
> > > +        *  meet the following requirements:
> > > +        *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
> > > +        *  270                    | 320 or higher
> > > +        *  162                    | 200 or higher"
> > > +        */
> > > +       if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> > > +           intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
> > > +               min_cdclk = max(crtc_state->port_clock, min_cdclk);
> > 
> > I tracked port_clock down to being the dp link clock (162 or 270) so
> > that part of the story checks out.
> > 
> > Judging by the rest of the function, I buy that the cdclk and link clock
> > may be inscrutably tied together, and accept the test result that the
> > cdclk must be at least the link clock with audio enabled.
> > 
> > It may be that a corner case does require a higher frequency (rather
> > than just bumping from 266 to 270), but for here and now
> 
> Yeah there could be some extra headroom required. But our cdclk
> can only be 200, 266, 320 or 400 MHz (and 200 won't actually get used
> due to inexplicable display failure when try to use it). So in practice
> we going to actually get bumped 162->266 and 270->320 here. I should
> have expressed that better in the commit message.

Also, I didn't find an easy way to confirm the limited set of cdlck.
Hmm, actually I was looking at min_cdclk and didn't thin to compare that
against any table. Ah, adding a see vlv_calc_cdclk() might have helped
me put together the other side. Certainly adding more of a hint that
min_cdclk isn't the final clock would help :)
-Chris