From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sasha Levin Subject: [PATCH AUTOSEL 5.2 019/171] drm/amd/display: fix multi display seamless boot case Date: Thu, 18 Jul 2019 23:54:10 -0400 Message-ID: <20190719035643.14300-19-sashal@kernel.org> References: <20190719035643.14300-1-sashal@kernel.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190719035643.14300-1-sashal-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Sasha Levin , Aric Cyr , Anthony Koo , amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, Alex Deucher , Bhawanpreet Lakha RnJvbTogQW50aG9ueSBLb28gPGFudGhvbnkua29vQGFtZC5jb20+CgpbIFVwc3RyZWFtIGNvbW1p dCA0Y2Q3NWZmMDk2ZjRlZjQ5YzM0MzA5M2I1MmE5NTJmMjdhYmE3Nzk2IF0KCltXaHldClRoZXJl IGlzIGEgc2NlbmFyaW8gdGhhdCBjYXVzZXMgZURQIHRvIGJlY29tZSBibGFuayBpZgp0aGVyZSBh cmUgbXVsdGlwbGUgZGlzcGxheXMgY29ubmVjdGVkLCBhbmQgdGhlIGV4dGVybmFsCmRpc3BsYXkg aXMgc2V0IGFzIHRoZSBwcmltYXJ5IGRpc3BsYXkgc3VjaCB0aGF0IHRoZSBmaXJzdApmbGlwIGNv bWVzIHRvIHRoZSBleHRlcm5hbCBkaXNwbGF5LgoKSW4gdGhpcyBzY2VuYXJpbywgd2UgY2FsbCBv dXIgb3B0aW1pemUgZnVuY3Rpb24gYmVmb3JlCnRoZSBlRFAgZXZlbiBoYXMgYSBjaGFuY2UgdG8g ZmxpcC4KCltIb3ddClRoZXJlIGlzIGEgY2hlY2sgdGhhdCBwcmV2ZW50cyBiYW5kd2lkdGggb3B0 aW1pemUgZnJvbQpvY2N1cnJpbmcgYmVmb3JlIGZpcnN0IGZsaXAgaXMgY29tcGxldGUgb24gdGhl IHNlYW1sZXNzIGJvb3QKZGlzcGxheS4KQnV0IGFjdHVhbGx5IGl0IGFzc3VtZWQgdGhlIHNlYW1s ZXNzIGJvb3QgZGlzcGxheSBpcyB0aGUKZmlyc3Qgb25lIHRvIGZsaXAuIEJ1dCBpbiB0aGlzIHNj ZW5hcmlvIGl0IGlzIG5vdC4KTW9kaWZ5IHRoZSBjaGVjayB0byBlbnN1cmUgdGhlIHN0ZWFtIHdp dGggdGhlIHNlYW1sZXNzCmJvb3QgZmxhZyBzZXQgaXMgdGhlIG9uZSB0aGF0IGhhcyBjb21wbGV0 ZWQgdGhlIGZpcnN0IGZsaXAuCgpTaWduZWQtb2ZmLWJ5OiBBbnRob255IEtvbyA8YW50aG9ueS5r b29AYW1kLmNvbT4KUmV2aWV3ZWQtYnk6IEFyaWMgQ3lyIDxBcmljLkN5ckBhbWQuY29tPgpBY2tl ZC1ieTogQmhhd2FucHJlZXQgTGFraGEgPEJoYXdhbnByZWV0Lkxha2hhQGFtZC5jb20+ClNpZ25l ZC1vZmYtYnk6IEFsZXggRGV1Y2hlciA8YWxleGFuZGVyLmRldWNoZXJAYW1kLmNvbT4KU2lnbmVk LW9mZi1ieTogU2FzaGEgTGV2aW4gPHNhc2hhbEBrZXJuZWwub3JnPgotLS0KIGRyaXZlcnMvZ3B1 L2RybS9hbWQvZGlzcGxheS9kYy9jb3JlL2RjLmMgfCAxNCArKysrKysrKy0tLS0tLQogMSBmaWxl IGNoYW5nZWQsIDggaW5zZXJ0aW9ucygrKSwgNiBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9k cml2ZXJzL2dwdS9kcm0vYW1kL2Rpc3BsYXkvZGMvY29yZS9kYy5jIGIvZHJpdmVycy9ncHUvZHJt L2FtZC9kaXNwbGF5L2RjL2NvcmUvZGMuYwppbmRleCAxOGM3NzVhOTUwY2MuLmVlNmI2NDYxODBi NiAxMDA2NDQKLS0tIGEvZHJpdmVycy9ncHUvZHJtL2FtZC9kaXNwbGF5L2RjL2NvcmUvZGMuYwor KysgYi9kcml2ZXJzL2dwdS9kcm0vYW1kL2Rpc3BsYXkvZGMvY29yZS9kYy5jCkBAIC0xMTM4LDkg KzExMzgsNiBAQCBzdGF0aWMgZW51bSBkY19zdGF0dXMgZGNfY29tbWl0X3N0YXRlX25vX2NoZWNr KHN0cnVjdCBkYyAqZGMsIHN0cnVjdCBkY19zdGF0ZSAqYwogCQljb25zdCBzdHJ1Y3QgZGNfbGlu ayAqbGluayA9IGNvbnRleHQtPnN0cmVhbXNbaV0tPmxpbms7CiAJCXN0cnVjdCBkY19zdHJlYW1f c3RhdHVzICpzdGF0dXM7CiAKLQkJaWYgKGNvbnRleHQtPnN0cmVhbXNbaV0tPmFwcGx5X3NlYW1s ZXNzX2Jvb3Rfb3B0aW1pemF0aW9uKQotCQkJY29udGV4dC0+c3RyZWFtc1tpXS0+YXBwbHlfc2Vh bWxlc3NfYm9vdF9vcHRpbWl6YXRpb24gPSBmYWxzZTsKLQogCQlpZiAoIWNvbnRleHQtPnN0cmVh bXNbaV0tPm1vZGVfY2hhbmdlZCkKIAkJCWNvbnRpbnVlOwogCkBAIC0xNzkyLDEwICsxNzg5LDE1 IEBAIHN0YXRpYyB2b2lkIGNvbW1pdF9wbGFuZXNfZm9yX3N0cmVhbShzdHJ1Y3QgZGMgKmRjLAog CWlmIChkYy0+b3B0aW1pemVfc2VhbWxlc3NfYm9vdCAmJiBzdXJmYWNlX2NvdW50ID4gMCkgewog CQkvKiBPcHRpbWl6ZSBzZWFtbGVzcyBib290IGZsYWcga2VlcHMgY2xvY2tzIGFuZCB3YXRlcm1h cmtzIGhpZ2ggdW50aWwKIAkJICogZmlyc3QgZmxpcC4gQWZ0ZXIgZmlyc3QgZmxpcCwgb3B0aW1p emF0aW9uIGlzIHJlcXVpcmVkIHRvIGxvd2VyCi0JCSAqIGJhbmR3aWR0aC4KKwkJICogYmFuZHdp ZHRoLiBJbXBvcnRhbnQgdG8gbm90ZSB0aGF0IGl0IGlzIGV4cGVjdGVkIFVFRkkgd2lsbAorCQkg KiBvbmx5IGxpZ2h0IHVwIGEgc2luZ2xlIGRpc3BsYXkgb24gUE9TVCwgdGhlcmVmb3JlIHdlIG9u bHkgZXhwZWN0CisJCSAqIG9uZSBzdHJlYW0gd2l0aCBzZWFtbGVzcyBib290IGZsYWcgc2V0Lgog CQkgKi8KLQkJZGMtPm9wdGltaXplX3NlYW1sZXNzX2Jvb3QgPSBmYWxzZTsKLQkJZGMtPm9wdGlt aXplZF9yZXF1aXJlZCA9IHRydWU7CisJCWlmIChzdHJlYW0tPmFwcGx5X3NlYW1sZXNzX2Jvb3Rf b3B0aW1pemF0aW9uKSB7CisJCQlzdHJlYW0tPmFwcGx5X3NlYW1sZXNzX2Jvb3Rfb3B0aW1pemF0 aW9uID0gZmFsc2U7CisJCQlkYy0+b3B0aW1pemVfc2VhbWxlc3NfYm9vdCA9IGZhbHNlOworCQkJ ZGMtPm9wdGltaXplZF9yZXF1aXJlZCA9IHRydWU7CisJCX0KIAl9CiAKIAlpZiAodXBkYXRlX3R5 cGUgPT0gVVBEQVRFX1RZUEVfRlVMTCAmJiAhZGMtPm9wdGltaXplX3NlYW1sZXNzX2Jvb3QpIHsK LS0gCjIuMjAuMQoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X18KYW1kLWdmeCBtYWlsaW5nIGxpc3QKYW1kLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0 cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbWQtZ2Z4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0740C76188 for ; Fri, 19 Jul 2019 03:57:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id A26F02082E for ; Fri, 19 Jul 2019 03:57:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563508655; bh=oZq74vOU69k95kJgkuxq8/TZXIrComA3tcoACkgcGz8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=HGMzgR3Bj4Qv9njhNaPs08ISgoU5RSvDeclspj8pv/+tvrJuBsq+KaTKeZhgl9Npn uRJDO57+Anh04Cxhk18Rx7K5D9SWHrpUWBrhovr9x9gvTg/4v8D6YjLbui5L4g85w4 lkZnBJ+o4b9rnCNPA5O/i06wQUGaWWtrVDizGKFU= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727406AbfGSD5e (ORCPT ); Thu, 18 Jul 2019 23:57:34 -0400 Received: from mail.kernel.org ([198.145.29.99]:56760 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727356AbfGSD5c (ORCPT ); Thu, 18 Jul 2019 23:57:32 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id C8EE921852; Fri, 19 Jul 2019 03:57:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1563508650; bh=oZq74vOU69k95kJgkuxq8/TZXIrComA3tcoACkgcGz8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ovkiMuWlOdx5taxJj1PjkknHXxKMKOTShefC/J+8Mua4jfONv4lTcyAPDJiliyB4W zm4XpktlqWDPZ5+6KCNlMKTriBLaWGv8/w+mMG16h2+XHAQxLChys5DhCXSlGUa7es zdJKDnKWu6BWvRct4g0AyfH0p8+rkmoOjQLQmN1Q= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Anthony Koo , Aric Cyr , Bhawanpreet Lakha , Alex Deucher , Sasha Levin , amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: [PATCH AUTOSEL 5.2 019/171] drm/amd/display: fix multi display seamless boot case Date: Thu, 18 Jul 2019 23:54:10 -0400 Message-Id: <20190719035643.14300-19-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190719035643.14300-1-sashal@kernel.org> References: <20190719035643.14300-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anthony Koo [ Upstream commit 4cd75ff096f4ef49c343093b52a952f27aba7796 ] [Why] There is a scenario that causes eDP to become blank if there are multiple displays connected, and the external display is set as the primary display such that the first flip comes to the external display. In this scenario, we call our optimize function before the eDP even has a chance to flip. [How] There is a check that prevents bandwidth optimize from occurring before first flip is complete on the seamless boot display. But actually it assumed the seamless boot display is the first one to flip. But in this scenario it is not. Modify the check to ensure the steam with the seamless boot flag set is the one that has completed the first flip. Signed-off-by: Anthony Koo Reviewed-by: Aric Cyr Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher Signed-off-by: Sasha Levin --- drivers/gpu/drm/amd/display/dc/core/dc.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 18c775a950cc..ee6b646180b6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1138,9 +1138,6 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c const struct dc_link *link = context->streams[i]->link; struct dc_stream_status *status; - if (context->streams[i]->apply_seamless_boot_optimization) - context->streams[i]->apply_seamless_boot_optimization = false; - if (!context->streams[i]->mode_changed) continue; @@ -1792,10 +1789,15 @@ static void commit_planes_for_stream(struct dc *dc, if (dc->optimize_seamless_boot && surface_count > 0) { /* Optimize seamless boot flag keeps clocks and watermarks high until * first flip. After first flip, optimization is required to lower - * bandwidth. + * bandwidth. Important to note that it is expected UEFI will + * only light up a single display on POST, therefore we only expect + * one stream with seamless boot flag set. */ - dc->optimize_seamless_boot = false; - dc->optimized_required = true; + if (stream->apply_seamless_boot_optimization) { + stream->apply_seamless_boot_optimization = false; + dc->optimize_seamless_boot = false; + dc->optimized_required = true; + } } if (update_type == UPDATE_TYPE_FULL && !dc->optimize_seamless_boot) { -- 2.20.1