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[79.181.91.42]) by smtp.gmail.com with ESMTPSA id z1sm22305728qkg.103.2019.07.23.03.10.56 (version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256); Tue, 23 Jul 2019 03:10:58 -0700 (PDT) Date: Tue, 23 Jul 2019 06:10:53 -0400 From: "Michael S. Tsirkin" To: "Zhangbo (Oscar)" Message-ID: <20190723061015-mutt-send-email-mst@kernel.org> References: <0259E1C966E8C54AA93AA2B1240828E672DF3D45@dggeml509-mbx.china.huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0259E1C966E8C54AA93AA2B1240828E672DF3D45@dggeml509-mbx.china.huawei.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.85.160.195 Subject: Re: [Qemu-devel] [PATCH v2] pcie: fix device unplug timeout X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fangying , "philmd@redhat.com" , "qemu-devel@nongnu.org" , "limingwang \(A\)" , "dengkai \(A\)" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Jul 23, 2019 at 09:33:43AM +0000, Zhangbo (Oscar) wrote: > If the linux kernel only receives an ABP event during pcie unplug, it will sleep 5s > to expect a PDC event, which will cause device unplug timeout. > > In the meanwhile, if the kernel only receives a PDC event during the unplug, it > will wait for at least 1 second before checking card present as data link layer > state changed (link down) event reported prior to presence detect changed > (card is not present). > > Therefore we can send both ABP and PDC events to the kernel in unplug process > to avoid unplug timeout. > > Signed-off-by: Li Mingwang > Signed-off-by: Fang Ying > Signed-off-by: Zhang Bo I responded on v1 before seeing v2. As there's no change to patch or commit log, same comments apply. > --- > hw/pci/pcie.c | 8 ++------ > include/hw/pci/pcie.h | 1 - > 2 files changed, 2 insertions(+), 7 deletions(-) > > diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c > index 174f392..a800f23 100644 > --- a/hw/pci/pcie.c > +++ b/hw/pci/pcie.c > @@ -485,7 +485,8 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev, > PCI_EXP_LNKSTA_DLLLA); > } > > - pcie_cap_slot_push_attention_button(PCI_DEVICE(hotplug_dev)); > + pcie_cap_slot_event(PCI_DEVICE(hotplug_dev), > + PCI_EXP_HP_EV_PDC | PCI_EXP_HP_EV_ABP); > } > > /* pci express slot for pci express root/downstream port > @@ -701,11 +702,6 @@ int pcie_cap_slot_post_load(void *opaque, int version_id) > return 0; > } > > -void pcie_cap_slot_push_attention_button(PCIDevice *dev) > -{ > - pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); > -} > - > /* root control/capabilities/status. PME isn't emulated for now */ > void pcie_cap_root_init(PCIDevice *dev) > { > diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h > index 8cf3361..0975a54 100644 > --- a/include/hw/pci/pcie.h > +++ b/include/hw/pci/pcie.h > @@ -112,7 +112,6 @@ void pcie_cap_slot_write_config(PCIDevice *dev, > uint16_t old_slt_ctl, uint16_t old_slt_sta, > uint32_t addr, uint32_t val, int len); > int pcie_cap_slot_post_load(void *opaque, int version_id); > -void pcie_cap_slot_push_attention_button(PCIDevice *dev); > > void pcie_cap_root_init(PCIDevice *dev); > void pcie_cap_root_reset(PCIDevice *dev); > -- > 1.8.3.1