From: Christoph Hellwig <hch@infradead.org>
To: Sreekanth Reddy <sreekanth.reddy@broadcom.com>
Cc: Christoph Hellwig <hch@infradead.org>,
Suganath Prabu <suganath-prabu.subramani@broadcom.com>,
linux-scsi <linux-scsi@vger.kernel.org>,
stable@vger.kernel.org,
Sathya Prakash <Sathya.Prakash@broadcom.com>,
Kashyap Desai <kashyap.desai@broadcom.com>
Subject: Re: [PATCH] mpt3sas: Use 63-bit DMA addressing on SAS35 HBA
Date: Mon, 29 Jul 2019 23:38:45 -0700 [thread overview]
Message-ID: <20190730063845.GA16355@infradead.org> (raw)
In-Reply-To: <CAK=zhgrWW_vOkXKRYRbiMdHgiT7u=Ra_pCkO_HkmQrCdVXfJBQ@mail.gmail.com>
On Mon, Jul 29, 2019 at 05:25:35PM +0530, Sreekanth Reddy wrote:
>
> I agree with your above statement. But it is also possible that
> 0xFFFFFFFF-FFFFFFFF falls under the DMA able range, e.g. SGE's start
> address is 0xFFFFFFFF-FFFF000 and data length is 0x1000 bytes. So when
> HBA tries to DMA the data at 0xFFFFFFFF-FFFFFFFF location then it will
> faults the firmware due to it's hardware design.
>
> We have observed above example's SGE address and length on AMD systems
> with SME & IOMMU enabled.
Ok. Please slightly update the changelog to say dma ranges instead
of a dma address, as that implicies the addr field in the sg to me.
Otherwise looks ok:
Reviewed-by: Christoph Hellwig <hch@lst.de>
next prev parent reply other threads:[~2019-07-30 6:38 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-26 10:00 [PATCH] mpt3sas: Use 63-bit DMA addressing on SAS35 HBA Suganath Prabu
2019-07-26 10:20 ` Greg KH
2019-07-26 14:27 ` Christoph Hellwig
2019-07-29 11:55 ` Sreekanth Reddy
2019-07-30 6:38 ` Christoph Hellwig [this message]
-- strict thread matches above, loose matches on Subject: below --
2019-07-31 9:58 Suganath Prabu
2019-07-31 9:58 ` Suganath Prabu
2019-08-05 11:59 ` Greg KH
2019-07-31 10:08 ` Greg KH
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