All of lore.kernel.org
 help / color / mirror / Atom feed
From: Dmitry Osipenko <digetx@gmail.com>
To: Rob Herring <robh+dt@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Joseph Lo <josephl@nvidia.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Stephen Boyd <sboyd@kernel.org>
Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v9 05/15] memory: tegra20-emc: Pre-configure debug register
Date: Tue, 30 Jul 2019 19:56:08 +0300	[thread overview]
Message-ID: <20190730165618.10122-6-digetx@gmail.com> (raw)
In-Reply-To: <20190730165618.10122-1-digetx@gmail.com>

The driver expects certain debug features to be disabled in order to
work properly. Let's disable them explicitly for consistency and to not
rely on a boot state.

Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/memory/tegra/tegra20-emc.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/drivers/memory/tegra/tegra20-emc.c b/drivers/memory/tegra/tegra20-emc.c
index 1ce351dd5461..85c24f285fd4 100644
--- a/drivers/memory/tegra/tegra20-emc.c
+++ b/drivers/memory/tegra/tegra20-emc.c
@@ -22,6 +22,7 @@
 
 #define EMC_INTSTATUS				0x000
 #define EMC_INTMASK				0x004
+#define EMC_DBG					0x008
 #define EMC_TIMING_CONTROL			0x028
 #define EMC_RC					0x02c
 #define EMC_RFC					0x030
@@ -80,6 +81,12 @@
 #define EMC_REFRESH_OVERFLOW_INT		BIT(3)
 #define EMC_CLKCHANGE_COMPLETE_INT		BIT(4)
 
+#define EMC_DBG_READ_MUX_ASSEMBLY		BIT(0)
+#define EMC_DBG_WRITE_MUX_ACTIVE		BIT(1)
+#define EMC_DBG_FORCE_UPDATE			BIT(2)
+#define EMC_DBG_READ_DQM_CTRL			BIT(9)
+#define EMC_DBG_CFG_PRIORITY			BIT(24)
+
 static const u16 emc_timing_registers[] = {
 	EMC_RC,
 	EMC_RFC,
@@ -396,7 +403,7 @@ tegra_emc_find_node_by_ram_code(struct device *dev)
 static int emc_setup_hw(struct tegra_emc *emc)
 {
 	u32 intmask = EMC_REFRESH_OVERFLOW_INT | EMC_CLKCHANGE_COMPLETE_INT;
-	u32 emc_cfg;
+	u32 emc_cfg, emc_dbg;
 
 	emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
 
@@ -419,6 +426,14 @@ static int emc_setup_hw(struct tegra_emc *emc)
 	writel_relaxed(intmask, emc->regs + EMC_INTMASK);
 	writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
 
+	/* ensure that unwanted debug features are disabled */
+	emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
+	emc_dbg |= EMC_DBG_CFG_PRIORITY;
+	emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
+	emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
+	emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
+	writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
+
 	return 0;
 }
 
-- 
2.22.0


  parent reply	other threads:[~2019-07-30 16:59 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-30 16:56 [PATCH v9 00/15] memory: tegra: Introduce Tegra30 EMC driver Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 01/15] clk: tegra20/30: Add custom EMC clock implementation Dmitry Osipenko
2019-08-01 11:10   ` Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 02/15] memory: tegra20-emc: Drop setting EMC rate to max on probe Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 03/15] memory: tegra20-emc: Adapt for clock driver changes Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 04/15] memory: tegra20-emc: Include io.h instead of iopoll.h Dmitry Osipenko
2019-07-30 16:56 ` Dmitry Osipenko [this message]
2019-07-30 16:56 ` [PATCH v9 06/15] memory: tegra20-emc: Print a brief info message about the timings Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 07/15] memory: tegra20-emc: Increase handshake timeout Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 08/15] memory: tegra20-emc: wait_for_completion_timeout() doesn't return error Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 09/15] dt-bindings: memory: tegra30: Convert to Tegra124 YAML Dmitry Osipenko
2019-08-01 16:25   ` Rob Herring
2019-08-01 17:52     ` Dmitry Osipenko
2019-08-01 18:06       ` Rob Herring
2019-07-30 16:56 ` [PATCH v9 10/15] dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 11/15] dt-bindings: memory: Add binding for NVIDIA Tegra30 External " Dmitry Osipenko
2019-08-01 11:05   ` Dmitry Osipenko
2019-08-01 18:11   ` Rob Herring
2019-08-01 18:35     ` Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 12/15] memory: tegra: Introduce Tegra30 EMC driver Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 13/15] memory: tegra: Ensure timing control debug features are disabled Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 14/15] memory: tegra: Consolidate registers definition into common header Dmitry Osipenko
2019-07-30 16:56 ` [PATCH v9 15/15] ARM: dts: tegra30: Add External Memory Controller node Dmitry Osipenko

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190730165618.10122-6-digetx@gmail.com \
    --to=digetx@gmail.com \
    --cc=devicetree@vger.kernel.org \
    --cc=jonathanh@nvidia.com \
    --cc=josephl@nvidia.com \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=mturquette@baylibre.com \
    --cc=pdeschrijver@nvidia.com \
    --cc=pgaikwad@nvidia.com \
    --cc=robh+dt@kernel.org \
    --cc=sboyd@kernel.org \
    --cc=thierry.reding@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.