From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06CB0C433FF for ; Fri, 2 Aug 2019 13:21:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id C67DB2173E for ; Fri, 2 Aug 2019 13:21:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1564752098; bh=Z3+DlEgPPOfyTqSMYWiDIsaMH7bYjj3YAxmRj4cC21E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=ZrzbKP9WetnuuVkwZudDUHarRYczZxkhFZypHSfUHimYmb7Z6q98tYLF2OJFVvIRW Y0KLHfsAltyNa2M9Eu/ctopYkRp1+5Ko0GFMlTcu/ePr5jI7AqWLE8mBz5dHE+2IdL i4gTmqktMQ/8Ii8TguKlAVsk9g2tyl01cRVqWPJw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393531AbfHBNVd (ORCPT ); Fri, 2 Aug 2019 09:21:33 -0400 Received: from mail.kernel.org ([198.145.29.99]:59810 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2393556AbfHBNVU (ORCPT ); Fri, 2 Aug 2019 09:21:20 -0400 Received: from sasha-vm.mshome.net (c-73-47-72-35.hsd1.nh.comcast.net [73.47.72.35]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 001D02173E; Fri, 2 Aug 2019 13:21:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1564752079; bh=Z3+DlEgPPOfyTqSMYWiDIsaMH7bYjj3YAxmRj4cC21E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PeGbkyne4hjVzsD8BRlnd8sgaQMQeSbUTtq4sGfIRKyWWTcXCcooWt2I9XIk01dL2 UKNjoskG0KTJgQCIB+nJFYAQY9bX6j9TuZee5Bfpq7mOVXynToHkewL4BwT7xVhsRb 9yJ1TleS0L7/E4HScu5cs+Sb6mcMWJP2+AxOnwJg= From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Shubhashree Dhar , Sean Paul , Sasha Levin , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH AUTOSEL 5.2 41/76] drm/msm/dpu: Correct dpu encoder spinlock initialization Date: Fri, 2 Aug 2019 09:19:15 -0400 Message-Id: <20190802131951.11600-41-sashal@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190802131951.11600-1-sashal@kernel.org> References: <20190802131951.11600-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Shubhashree Dhar [ Upstream commit 2e7b801eadbf327bf61041c943e5c44a5de4b0e5 ] dpu encoder spinlock should be initialized during dpu encoder init instead of dpu encoder setup which is part of modeset init. Signed-off-by: Shubhashree Dhar [seanpaul resolved conflict in old init removal and revised the commit message] Signed-off-by: Sean Paul Link: https://patchwork.freedesktop.org/patch/msgid/1561357632-15361-1-git-send-email-dhar@codeaurora.org Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 0ea1501966594..c62f7abcf509c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2226,8 +2226,6 @@ int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, if (ret) goto fail; - spin_lock_init(&dpu_enc->enc_spinlock); - atomic_set(&dpu_enc->frame_done_timeout_ms, 0); timer_setup(&dpu_enc->frame_done_timer, dpu_encoder_frame_done_timeout, 0); @@ -2281,6 +2279,7 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, drm_encoder_helper_add(&dpu_enc->base, &dpu_encoder_helper_funcs); + spin_lock_init(&dpu_enc->enc_spinlock); dpu_enc->enabled = false; return &dpu_enc->base; -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sasha Levin Subject: [PATCH AUTOSEL 5.2 41/76] drm/msm/dpu: Correct dpu encoder spinlock initialization Date: Fri, 2 Aug 2019 09:19:15 -0400 Message-ID: <20190802131951.11600-41-sashal@kernel.org> References: <20190802131951.11600-1-sashal@kernel.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20190802131951.11600-1-sashal-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Cc: Sasha Levin , Shubhashree Dhar , linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, Sean Paul , freedreno-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org List-Id: dri-devel@lists.freedesktop.org RnJvbTogU2h1Ymhhc2hyZWUgRGhhciA8ZGhhckBjb2RlYXVyb3JhLm9yZz4KClsgVXBzdHJlYW0g Y29tbWl0IDJlN2I4MDFlYWRiZjMyN2JmNjEwNDFjOTQzZTVjNDRhNWRlNGIwZTUgXQoKZHB1IGVu Y29kZXIgc3BpbmxvY2sgc2hvdWxkIGJlIGluaXRpYWxpemVkIGR1cmluZyBkcHUgZW5jb2Rlcgpp bml0IGluc3RlYWQgb2YgZHB1IGVuY29kZXIgc2V0dXAgd2hpY2ggaXMgcGFydCBvZiBtb2Rlc2V0 IGluaXQuCgpTaWduZWQtb2ZmLWJ5OiBTaHViaGFzaHJlZSBEaGFyIDxkaGFyQGNvZGVhdXJvcmEu b3JnPgpbc2VhbnBhdWwgcmVzb2x2ZWQgY29uZmxpY3QgaW4gb2xkIGluaXQgcmVtb3ZhbCBhbmQg cmV2aXNlZCB0aGUgY29tbWl0IG1lc3NhZ2VdClNpZ25lZC1vZmYtYnk6IFNlYW4gUGF1bCA8c2Vh bnBhdWxAY2hyb21pdW0ub3JnPgpMaW5rOiBodHRwczovL3BhdGNod29yay5mcmVlZGVza3RvcC5v cmcvcGF0Y2gvbXNnaWQvMTU2MTM1NzYzMi0xNTM2MS0xLWdpdC1zZW5kLWVtYWlsLWRoYXJAY29k ZWF1cm9yYS5vcmcKU2lnbmVkLW9mZi1ieTogU2FzaGEgTGV2aW4gPHNhc2hhbEBrZXJuZWwub3Jn PgotLS0KIGRyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9lbmNvZGVyLmMgfCAzICst LQogMSBmaWxlIGNoYW5nZWQsIDEgaW5zZXJ0aW9uKCspLCAyIGRlbGV0aW9ucygtKQoKZGlmZiAt LWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9kcHUxL2RwdV9lbmNvZGVyLmMgYi9kcml2 ZXJzL2dwdS9kcm0vbXNtL2Rpc3AvZHB1MS9kcHVfZW5jb2Rlci5jCmluZGV4IDBlYTE1MDE5NjY1 OTQuLmM2MmY3YWJjZjUwOWMgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9tc20vZGlzcC9k cHUxL2RwdV9lbmNvZGVyLmMKKysrIGIvZHJpdmVycy9ncHUvZHJtL21zbS9kaXNwL2RwdTEvZHB1 X2VuY29kZXIuYwpAQCAtMjIyNiw4ICsyMjI2LDYgQEAgaW50IGRwdV9lbmNvZGVyX3NldHVwKHN0 cnVjdCBkcm1fZGV2aWNlICpkZXYsIHN0cnVjdCBkcm1fZW5jb2RlciAqZW5jLAogCWlmIChyZXQp CiAJCWdvdG8gZmFpbDsKIAotCXNwaW5fbG9ja19pbml0KCZkcHVfZW5jLT5lbmNfc3BpbmxvY2sp OwotCiAJYXRvbWljX3NldCgmZHB1X2VuYy0+ZnJhbWVfZG9uZV90aW1lb3V0X21zLCAwKTsKIAl0 aW1lcl9zZXR1cCgmZHB1X2VuYy0+ZnJhbWVfZG9uZV90aW1lciwKIAkJCWRwdV9lbmNvZGVyX2Zy YW1lX2RvbmVfdGltZW91dCwgMCk7CkBAIC0yMjgxLDYgKzIyNzksNyBAQCBzdHJ1Y3QgZHJtX2Vu Y29kZXIgKmRwdV9lbmNvZGVyX2luaXQoc3RydWN0IGRybV9kZXZpY2UgKmRldiwKIAogCWRybV9l bmNvZGVyX2hlbHBlcl9hZGQoJmRwdV9lbmMtPmJhc2UsICZkcHVfZW5jb2Rlcl9oZWxwZXJfZnVu Y3MpOwogCisJc3Bpbl9sb2NrX2luaXQoJmRwdV9lbmMtPmVuY19zcGlubG9jayk7CiAJZHB1X2Vu Yy0+ZW5hYmxlZCA9IGZhbHNlOwogCiAJcmV0dXJuICZkcHVfZW5jLT5iYXNlOwotLSAKMi4yMC4x CgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpGcmVlZHJl bm8gbWFpbGluZyBsaXN0CkZyZWVkcmVub0BsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9s aXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9mcmVlZHJlbm8=