All of lore.kernel.org
 help / color / mirror / Atom feed
From: Christoph Hellwig <hch@infradead.org>
To: "Koenig, Christian" <Christian.Koenig@amd.com>
Cc: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"kernel-build-reports@lists.linaro.org"
	<kernel-build-reports@lists.linaro.org>,
	"Zhou1, Tao" <Tao.Zhou1@amd.com>,
	"amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>,
	Christoph Hellwig <hch@infradead.org>,
	"broonie@kernel.org" <broonie@kernel.org>,
	"linux-next@vger.kernel.org" <linux-next@vger.kernel.org>,
	"Deucher, Alexander" <Alexander.Deucher@amd.com>,
	"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
	"Li, Dennis" <Dennis.Li@amd.com>,
	"Zhang, Hawking" <Hawking.Zhang@amd.com>
Subject: Re: [PATCH] drm/amdgpu: replace readq/writeq with atomic64 operations
Date: Wed, 7 Aug 2019 06:00:43 -0700	[thread overview]
Message-ID: <20190807130043.GA6023@infradead.org> (raw)
In-Reply-To: <18cd9fa5-2d87-2f41-b5fa-927b9790287d@amd.com>

On Wed, Aug 07, 2019 at 10:55:01AM +0000, Koenig, Christian wrote:
> >> Essentially writeq/readq doesn't seems to be available on all
> >> architectures either.
> > writeq/readq are provided whenever the CPU actually supports 64-bit
> > atomic loads and stores.
> 
> Is there a config option which we can make the driver depend on?
> 
> I mean that ARM doesn't support 64bit atomic loads and stores on MMIO is 
> quite a boomer for us.

The model is to cheack if readq/writeq are defined, and if not to
include the one of io-64-nonatomic-hi-lo.h or io-64-nonatomic-lo-hi.h.
The reason for that is that hardware is supposed to be able to deal with
two 32-bit writes, but it depends on the hardware if the lower or upper
half is what commits the write.

The only 32-bit platform that claims support for readq/writeq is sh,
and I have doubts if that actually works as expected.

WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@infradead.org>
To: "Koenig, Christian" <Christian.Koenig@amd.com>
Cc: Christoph Hellwig <hch@infradead.org>,
	"Zhou1, Tao" <Tao.Zhou1@amd.com>,
	"amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>,
	"Deucher, Alexander" <Alexander.Deucher@amd.com>,
	"Zhang, Hawking" <Hawking.Zhang@amd.com>,
	"Li, Dennis" <Dennis.Li@amd.com>,
	"broonie@kernel.org" <broonie@kernel.org>,
	"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
	"linux-next@vger.kernel.org" <linux-next@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"kernel-build-reports@lists.linaro.org" 
	<kernel-build-reports@lists.linaro.org>
Subject: Re: [PATCH] drm/amdgpu: replace readq/writeq with atomic64 operations
Date: Wed, 7 Aug 2019 06:00:43 -0700	[thread overview]
Message-ID: <20190807130043.GA6023@infradead.org> (raw)
In-Reply-To: <18cd9fa5-2d87-2f41-b5fa-927b9790287d@amd.com>

On Wed, Aug 07, 2019 at 10:55:01AM +0000, Koenig, Christian wrote:
> >> Essentially writeq/readq doesn't seems to be available on all
> >> architectures either.
> > writeq/readq are provided whenever the CPU actually supports 64-bit
> > atomic loads and stores.
> 
> Is there a config option which we can make the driver depend on?
> 
> I mean that ARM doesn't support 64bit atomic loads and stores on MMIO is 
> quite a boomer for us.

The model is to cheack if readq/writeq are defined, and if not to
include the one of io-64-nonatomic-hi-lo.h or io-64-nonatomic-lo-hi.h.
The reason for that is that hardware is supposed to be able to deal with
two 32-bit writes, but it depends on the hardware if the lower or upper
half is what commits the write.

The only 32-bit platform that claims support for readq/writeq is sh,
and I have doubts if that actually works as expected.

WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@infradead.org>
To: "Koenig, Christian" <Christian.Koenig@amd.com>
Cc: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"kernel-build-reports@lists.linaro.org"
	<kernel-build-reports@lists.linaro.org>,
	"Zhou1, Tao" <Tao.Zhou1@amd.com>,
	"amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>,
	Christoph Hellwig <hch@infradead.org>,
	"broonie@kernel.org" <broonie@kernel.org>,
	"linux-next@vger.kernel.org" <linux-next@vger.kernel.org>,
	"Deucher, Alexander" <Alexander.Deucher@amd.com>,
	"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
	"Li, Dennis" <Dennis.Li@amd.com>,
	"Zhang, Hawking" <Hawking.Zhang@amd.com>
Subject: Re: [PATCH] drm/amdgpu: replace readq/writeq with atomic64 operations
Date: Wed, 7 Aug 2019 06:00:43 -0700	[thread overview]
Message-ID: <20190807130043.GA6023@infradead.org> (raw)
In-Reply-To: <18cd9fa5-2d87-2f41-b5fa-927b9790287d@amd.com>

On Wed, Aug 07, 2019 at 10:55:01AM +0000, Koenig, Christian wrote:
> >> Essentially writeq/readq doesn't seems to be available on all
> >> architectures either.
> > writeq/readq are provided whenever the CPU actually supports 64-bit
> > atomic loads and stores.
> 
> Is there a config option which we can make the driver depend on?
> 
> I mean that ARM doesn't support 64bit atomic loads and stores on MMIO is 
> quite a boomer for us.

The model is to cheack if readq/writeq are defined, and if not to
include the one of io-64-nonatomic-hi-lo.h or io-64-nonatomic-lo-hi.h.
The reason for that is that hardware is supposed to be able to deal with
two 32-bit writes, but it depends on the hardware if the lower or upper
half is what commits the write.

The only 32-bit platform that claims support for readq/writeq is sh,
and I have doubts if that actually works as expected.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-08-07 13:00 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-07  2:56 [PATCH] drm/amdgpu: replace readq/writeq with atomic64 operations Tao Zhou
2019-08-07  2:56 ` Tao Zhou
2019-08-07  2:56 ` Tao Zhou
2019-08-07  3:09 ` Jisheng Zhang
2019-08-07  3:09   ` Jisheng Zhang
2019-08-07  3:09   ` Jisheng Zhang
     [not found]   ` <20190807105759.58a28ef0-XW7BGIvHH6X931TTwiNRCw@public.gmane.org>
2019-08-07  4:02     ` Alex Deucher
2019-08-07  4:02       ` Alex Deucher
2019-08-07  4:02       ` Alex Deucher
     [not found] ` <20190807025640.682-1-tao.zhou1-5C7GfCeVMHo@public.gmane.org>
2019-08-07  4:03   ` Alex Deucher
2019-08-07  4:03     ` Alex Deucher
2019-08-07  4:03     ` Alex Deucher
2019-08-07  7:08 ` Christoph Hellwig
2019-08-07  7:08   ` Christoph Hellwig
2019-08-07  7:08   ` Christoph Hellwig
     [not found]   ` <20190807070834.GA24792-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
2019-08-07  8:53     ` Koenig, Christian
2019-08-07  8:53       ` Koenig, Christian
2019-08-07  8:53       ` Koenig, Christian
2019-08-07 10:41       ` Christoph Hellwig
2019-08-07 10:41         ` Christoph Hellwig
2019-08-07 10:41         ` Christoph Hellwig
2019-08-07 10:55         ` Koenig, Christian
2019-08-07 10:55           ` Koenig, Christian
2019-08-07 10:55           ` Koenig, Christian
2019-08-07 12:59           ` Mark Brown
2019-08-07 12:59             ` Mark Brown
     [not found]             ` <20190807125928.GC4048-7j8lgAiuQgnQXOPxS62xeg@public.gmane.org>
2019-08-07 13:00               ` Koenig, Christian
2019-08-07 13:00                 ` Koenig, Christian
2019-08-07 13:00                 ` Koenig, Christian
2019-08-07 13:07                 ` Christoph Hellwig
2019-08-07 13:07                   ` Christoph Hellwig
2019-08-07 13:07                   ` Christoph Hellwig
2019-08-07 13:00           ` Christoph Hellwig [this message]
2019-08-07 13:00             ` Christoph Hellwig
2019-08-07 13:00             ` Christoph Hellwig
     [not found]             ` <20190807130043.GA6023-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org>
2019-08-07 13:03               ` Koenig, Christian
2019-08-07 13:03                 ` Koenig, Christian
2019-08-07 13:03                 ` Koenig, Christian
     [not found]                 ` <c613ca25-4443-f275-ea8d-6d55af10ac77-5C7GfCeVMHo@public.gmane.org>
2019-08-07 18:00                   ` Alex Deucher
2019-08-07 18:00                     ` Alex Deucher
2019-08-07 18:00                     ` Alex Deucher
2019-08-08 19:25 ` Guenter Roeck
2019-08-08 19:25   ` Guenter Roeck
     [not found]   ` <20190808192535.GA18697-0h96xk9xTtrk1uMJSBkQmQ@public.gmane.org>
2019-08-08 19:33     ` Alex Deucher
2019-08-08 19:33       ` Alex Deucher
2019-08-08 19:33       ` Alex Deucher
     [not found]       ` <CADnq5_ONGvL0yMybsXCyYJO6zKRAi4aEPo8LwEwQjSP3aVbdJQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2019-08-09  9:04         ` Koenig, Christian
2019-08-09  9:04           ` Koenig, Christian
2019-08-09  9:04           ` Koenig, Christian

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190807130043.GA6023@infradead.org \
    --to=hch@infradead.org \
    --cc=Alexander.Deucher@amd.com \
    --cc=Christian.Koenig@amd.com \
    --cc=Dennis.Li@amd.com \
    --cc=Hawking.Zhang@amd.com \
    --cc=Tao.Zhou1@amd.com \
    --cc=akpm@linux-foundation.org \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=broonie@kernel.org \
    --cc=kernel-build-reports@lists.linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-next@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.