From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A6C5C0650F for ; Thu, 8 Aug 2019 07:54:06 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 519CC217D7 for ; Thu, 8 Aug 2019 07:54:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="LfPERobq" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 519CC217D7 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qX+sadBliMbt5o8dm0qBmvdrDpWBLm+qxPEERXLgJDk=; b=LfPERobqZuS5z7 HQCXFO2grPCmavo6nQ8mSzT7h5DNHbpM8NHcHHXuudMEv8TdC9/FneJS3xLn2oK1OyORbj8DDAc+6 nOUUb6RUoDUSjdaIrK/rsmqqoVzoHny2cS/v7LQGGKkOlk+hqbzpADjvKoQnnYjXIpk1Ujz7Ml6FD NPKi5Fn3ZG8HTsuGcgPrOsGtwH6pFcbSTrvVCCchEyOdJMPq6KGcdtLEcyRCCK3dvXYK7QggmqyCl 2cdeI0eeeM8urkVeWRXmZJBzYauYm3xjpXdgjLBSw+GVuW+gEfCk1MFeP2CnsWVwx4xoJu51/d6bD fNcQlIU1ZHsfO+0pcEHg==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hvdFH-0002zi-Dc; Thu, 08 Aug 2019 07:53:59 +0000 Received: from verein.lst.de ([213.95.11.211]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hvdFE-0002zO-Av for linux-arm-kernel@lists.infradead.org; Thu, 08 Aug 2019 07:53:57 +0000 Received: by verein.lst.de (Postfix, from userid 2407) id EB68868B02; Thu, 8 Aug 2019 09:53:51 +0200 (CEST) Date: Thu, 8 Aug 2019 09:53:51 +0200 From: Christoph Hellwig To: Mark Rutland Subject: Re: [PATCH 1/2] drm: add cache support for arm64 Message-ID: <20190808075351.GC30308@lst.de> References: <20190805211451.20176-1-robdclark@gmail.com> <20190806084821.GA17129@lst.de> <20190806143457.GF475@lakrids.cambridge.arm.com> <20190807123807.GD54191@lakrids.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190807123807.GD54191@lakrids.cambridge.arm.com> User-Agent: Mutt/1.5.17 (2007-11-01) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190808_005356_535349_E650E342 X-CRM114-Status: GOOD ( 10.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Maxime Ripard , Catalin Marinas , David Airlie , Maarten Lankhorst , LKML , dri-devel , Sean Paul , Rob Clark , linux-arm-kernel@lists.infradead.org, Daniel Vetter , Greg Kroah-Hartman , Thomas Gleixner , Will Deacon , Christoph Hellwig , Allison Randal Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 07, 2019 at 01:38:08PM +0100, Mark Rutland wrote: > > I *believe* that there are not alias mappings (that I don't control > > myself) for pages coming from > > shmem_file_setup()/shmem_read_mapping_page().. > > AFAICT, that's regular anonymous memory, so there will be a cacheable > alias in the linear/direct map. Yes. Although shmem is in no way special in that regard. Even with the normal dma_alloc_coherent implementation on arm and arm64 we keep the cacheable alias in the direct mapping and just create a new non-cacheable one. The only exception are CMA allocations on 32-bit arm, which do get remapped to uncachable in place. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: Re: [PATCH 1/2] drm: add cache support for arm64 Date: Thu, 8 Aug 2019 09:53:51 +0200 Message-ID: <20190808075351.GC30308@lst.de> References: <20190805211451.20176-1-robdclark@gmail.com> <20190806084821.GA17129@lst.de> <20190806143457.GF475@lakrids.cambridge.arm.com> <20190807123807.GD54191@lakrids.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20190807123807.GD54191@lakrids.cambridge.arm.com> Sender: linux-kernel-owner@vger.kernel.org To: Mark Rutland Cc: Rob Clark , Christoph Hellwig , Rob Clark , dri-devel , Catalin Marinas , Will Deacon , Maarten Lankhorst , Maxime Ripard , Sean Paul , David Airlie , Daniel Vetter , Allison Randal , Greg Kroah-Hartman , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, LKML List-Id: dri-devel@lists.freedesktop.org On Wed, Aug 07, 2019 at 01:38:08PM +0100, Mark Rutland wrote: > > I *believe* that there are not alias mappings (that I don't control > > myself) for pages coming from > > shmem_file_setup()/shmem_read_mapping_page().. > > AFAICT, that's regular anonymous memory, so there will be a cacheable > alias in the linear/direct map. Yes. Although shmem is in no way special in that regard. Even with the normal dma_alloc_coherent implementation on arm and arm64 we keep the cacheable alias in the direct mapping and just create a new non-cacheable one. The only exception are CMA allocations on 32-bit arm, which do get remapped to uncachable in place.