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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hvdJj-0004sU-4G; Thu, 08 Aug 2019 07:58:35 +0000 Received: from verein.lst.de ([213.95.11.211]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hvdJf-0004s4-E9 for linux-arm-kernel@lists.infradead.org; Thu, 08 Aug 2019 07:58:32 +0000 Received: by verein.lst.de (Postfix, from userid 2407) id 3D39168B02; Thu, 8 Aug 2019 09:58:27 +0200 (CEST) Date: Thu, 8 Aug 2019 09:58:27 +0200 From: Christoph Hellwig To: Mark Rutland Subject: Re: [PATCH 1/2] drm: add cache support for arm64 Message-ID: <20190808075827.GD30308@lst.de> References: <20190805211451.20176-1-robdclark@gmail.com> <20190806084821.GA17129@lst.de> <20190806143457.GF475@lakrids.cambridge.arm.com> <20190807123807.GD54191@lakrids.cambridge.arm.com> <20190807164958.GA44765@lakrids.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190807164958.GA44765@lakrids.cambridge.arm.com> User-Agent: Mutt/1.5.17 (2007-11-01) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190808_005831_636476_6FEFBD2F X-CRM114-Status: GOOD ( 15.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Maxime Ripard , Catalin Marinas , David Airlie , Maarten Lankhorst , LKML , dri-devel , Sean Paul , Rob Clark , linux-arm-kernel@lists.infradead.org, Daniel Vetter , Greg Kroah-Hartman , Thomas Gleixner , Will Deacon , Christoph Hellwig , Allison Randal Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gV2VkLCBBdWcgMDcsIDIwMTkgYXQgMDU6NDk6NTlQTSArMDEwMCwgTWFyayBSdXRsYW5kIHdy b3RlOgo+IEknbSBmYWlybHkgY29uZmlkZW50IHRoYXQgdGhlIGxpbmVhci9kaXJlY3QgbWFwIGNh Y2hlYWJsZSBhbGlhcyBpcyBub3QKPiB0b3JuIGRvd24gd2hlbiBwYWdlcyBhcmUgYWxsb2NhdGVk LiBUaGUgZ25lZXJpYyBwYWdlIGFsbG9jYXRpb24gY29kZQo+IGRvZXNuJ3QgZG8gc28sIGFuZCBJ IHNlZSBub3RoaW5nIHRoZSBzaG1lbSBjb2RlIHRvIGRvIHNvLgoKSXQgaXMgbm90IHRvcm4gZG93 biBhbnl3aGVyZS4KCj4gRm9yIGFybTY0LCB3ZSBjYW4gdGVhciBkb3duIHBvcnRpb25zIG9mIHRo ZSBsaW5lYXIgbWFwLCBidXQgdGhhdCBoYXMgdG8KPiBiZSBkb25lIGV4cGxpY2l0bHksIGFuZCB0 aGlzIGlzIG9ubHkgcG9zc2libGUgd2hlbiB1c2luZyByb2RhdGFfZnVsbC4gSWYKPiBub3QgdXNp bmcgcm9kYXRhX2Z1bGwsIGl0IGlzIG5vdCBwb3NzaWJsZSB0byBkeW5hbWljYWxseSB0ZWFyIGRv d24gdGhlCj4gY2FjaGVhYmxlIGFsaWFzLgoKSW50ZXJlc3RpbmcuICBGb3IgdGhpcyBvciBuZXh0 IG1lcmdlIHdpbmRvdyBJIHBsYW4gdG8gYWRkIHN1cHBvcnQgdG8gdGhlCmdlbmVyaWMgRE1BIGNv ZGUgdG8gcmVtYXAgcGFnZXMgYXMgdW5jYWNoYWJsZSBpbiBwbGFjZSBiYXNlZCBvbiB0aGUKb3Bl bnJpc2MgY29kZS4gIEHRlSBmYXIgYXMgSSBjYW4gdGVsbCB0aGUgcmVxdWlyZW1lbnQgZm9yIHRo YXQgaXMKYmFzaWNhbGx5IGp1c3QgdGhhdCB0aGUga2VybmVsIGRpcmVjdCBtYXBwaW5nIGRvZXNu J3QgdXNlIFBNRCBvciBiaWdnZXIKbWFwcGluZyBzbyB0aGF0IGl0IHN1cHBvcnRzIGNoYW5naW5n IHByb3RlY3Rpb24gYml0cyBvbiBhIHBlci1QVEUgYmFzaXMuCklzIHRoYXQgdGhlIGNhc2Ugd2l0 aCBhcm02NCArIHJvZGF0YV9mdWxsPwoKPiA+IE15IHVuZGVyc3RhbmRpbmcgaXMgdGhhdCBhIGNh Y2hlYWJsZSBhbGlhcyBpcyAib2siLCB3aXRoIHNvbWUKPiA+IGNhdmVhdHMuLiBpZS4gdGhhdCB0 aGUgY2FjaGVhYmxlIGFsaWFzIGlzIG5vdCBhY2Nlc3NlZC4gIAo+IAo+IFVuZm9ydHVuYXRlbHks IHRoYXQgaXMgbm90IHRydWUuIFlvdSdsbCBvZnRlbiBnZXQgYXdheSB3aXRoIGl0IGluCj4gcHJh Y3RpY2UsIGJ1dCB0aGF0J3MgYSBtYXR0ZXIgb2YgcHJvYmFiaWxpdHkgcmF0aGVyIHRoYW4gYSBn dWFyYW50ZWUuCj4gCj4gWW91ICBjYW5ub3QgcHJldmVudCBhIENQVSBmcm9tIGFjY2Vzc2luZyBh IFZBIGFyYml0cmFyaWx5IChlLmcuIGFzIHRoZQo+IHJlc3VsdCBvZiB3aWxkIHNwZWN1bGF0aW9u KS4gVGhlIEFSTSBBUk0gKEFSTSBEREkgMDQ4N0UuYSkgcG9pbnRzIHRoaXMKPiBvdXQgZXhwbGlj aXRseToKCldlbGwsIGlmIHdlIHdhbnQgdG8gZml4IHRoaXMgcHJvcGVybHkgd2UnbGwgaGF2ZSB0 byByZW1hcCBpbiBwbGFjZQpmb3IgZG1hX2FsbG9jX2NvaGVyZW50IGFuZCBmcmllbmRzLgoKX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtl cm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0 dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5l bAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: Re: [PATCH 1/2] drm: add cache support for arm64 Date: Thu, 8 Aug 2019 09:58:27 +0200 Message-ID: <20190808075827.GD30308@lst.de> References: <20190805211451.20176-1-robdclark@gmail.com> <20190806084821.GA17129@lst.de> <20190806143457.GF475@lakrids.cambridge.arm.com> <20190807123807.GD54191@lakrids.cambridge.arm.com> <20190807164958.GA44765@lakrids.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: Content-Disposition: inline In-Reply-To: <20190807164958.GA44765@lakrids.cambridge.arm.com> Sender: linux-kernel-owner@vger.kernel.org To: Mark Rutland Cc: Rob Clark , Christoph Hellwig , Rob Clark , dri-devel , Catalin Marinas , Will Deacon , Maarten Lankhorst , Maxime Ripard , Sean Paul , David Airlie , Daniel Vetter , Allison Randal , Greg Kroah-Hartman , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, LKML List-Id: dri-devel@lists.freedesktop.org On Wed, Aug 07, 2019 at 05:49:59PM +0100, Mark Rutland wrote: > I'm fairly confident that the linear/direct map cacheable alias is not > torn down when pages are allocated. The gneeric page allocation code > doesn't do so, and I see nothing the shmem code to do so. It is not torn down anywhere. > For arm64, we can tear down portions of the linear map, but that has to > be done explicitly, and this is only possible when using rodata_full. If > not using rodata_full, it is not possible to dynamically tear down the > cacheable alias. Interesting. For this or next merge window I plan to add support to the generic DMA code to remap pages as uncachable in place based on the openrisc code. AŃ• far as I can tell the requirement for that is basically just that the kernel direct mapping doesn't use PMD or bigger mapping so that it supports changing protection bits on a per-PTE basis. Is that the case with arm64 + rodata_full? > > My understanding is that a cacheable alias is "ok", with some > > caveats.. ie. that the cacheable alias is not accessed. > > Unfortunately, that is not true. You'll often get away with it in > practice, but that's a matter of probability rather than a guarantee. > > You cannot prevent a CPU from accessing a VA arbitrarily (e.g. as the > result of wild speculation). The ARM ARM (ARM DDI 0487E.a) points this > out explicitly: Well, if we want to fix this properly we'll have to remap in place for dma_alloc_coherent and friends.