From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B48B6C0650F for ; Thu, 8 Aug 2019 09:55:20 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 85AE221479 for ; Thu, 8 Aug 2019 09:55:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Wgzxv4ad" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 85AE221479 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=aIu5xD86HXqp2bzssP5Us1fL8a/X/XS5DR+/dLp9bc8=; b=Wgzxv4adcIeHZH 6INDEYbpccTq3aUxyWZejltoL8dQk21x++PNFXTNgMiXWViPqoVOt8zR7opvXcmFB8u5vhDS7inUI XZN2GuB7DK4E07P6+5otD5aiQ1RWa/F9/7ubvjnm/CTnxXRFH2NI7EPKD69wRD0FvA6N98jnm1oZJ faj/Whe7UHe+l/aVYhM/KA8hdbhkBZ/XoDzGlZwXgHNxN/IJWqBPD9fvK7Bu5F3Zg2aVWT5XzyJxZ NMa50teCDqoFUz/udkLO5NxNPGUDCXZhkGrX8S3zwbFnfG1llmGYfu3266ba5iWgbK4Mu2EgODt02 vTuaZWYyyjKBDHbqN14w==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hvf8f-00061d-43; Thu, 08 Aug 2019 09:55:17 +0000 Received: from verein.lst.de ([213.95.11.211]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hvf8a-0005zn-Lz for linux-arm-kernel@lists.infradead.org; Thu, 08 Aug 2019 09:55:14 +0000 Received: by verein.lst.de (Postfix, from userid 2407) id 2AB2168AFE; Thu, 8 Aug 2019 11:55:07 +0200 (CEST) Date: Thu, 8 Aug 2019 11:55:06 +0200 From: Christoph Hellwig To: Daniel Vetter Subject: Re: [PATCH 1/2] drm: add cache support for arm64 Message-ID: <20190808095506.GA32621@lst.de> References: <20190805211451.20176-1-robdclark@gmail.com> <20190806084821.GA17129@lst.de> <20190806155044.GC25050@lst.de> <20190807062545.GF6627@lst.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190808_025512_869209_F90901B7 X-CRM114-Status: GOOD ( 11.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Maxime Ripard , Catalin Marinas , David Airlie , Maarten Lankhorst , LKML , dri-devel , Sean Paul , Rob Clark , Linux ARM , Greg Kroah-Hartman , Thomas Gleixner , Will Deacon , Christoph Hellwig , Allison Randal Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Aug 07, 2019 at 10:48:56AM +0200, Daniel Vetter wrote: > > other drm drivers how do they guarantee addressability without an > > iommu?) > > We use shmem to get at swappable pages. We generally just assume that > the gpu can get at those pages, but things fall apart in fun ways: > - some setups somehow inject bounce buffers. Some drivers just give > up, others try to allocate a pool of pages with dma_alloc_coherent. > - some devices are misdesigned and can't access as much as the cpu. We > allocate using GFP_DMA32 to fix that. Well, for shmem you can't really call allocators directly, right? One thing I have in my pipeline is a dma_alloc_pages API that allocates pages that are guaranteed to be addressably by the device or otherwise fail. But that doesn't really help with the shmem fs. > Also modern gpu apis pretty much assume you can malloc() and then use > that directly with the gpu. Which is fine as long as the GPU itself supports full 64-bit addressing (or always sits behind an iommu), and the platform doesn't impose addressing limit, which unfortunately some that are shipped right now still do :( But userspace malloc really means dma_map_* anyway, so not really relevant for memory allocations. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: Re: [PATCH 1/2] drm: add cache support for arm64 Date: Thu, 8 Aug 2019 11:55:06 +0200 Message-ID: <20190808095506.GA32621@lst.de> References: <20190805211451.20176-1-robdclark@gmail.com> <20190806084821.GA17129@lst.de> <20190806155044.GC25050@lst.de> <20190807062545.GF6627@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Daniel Vetter Cc: Christoph Hellwig , Rob Clark , Rob Clark , dri-devel , Catalin Marinas , Will Deacon , Maarten Lankhorst , Maxime Ripard , Sean Paul , David Airlie , Allison Randal , Greg Kroah-Hartman , Thomas Gleixner , Linux ARM , LKML List-Id: dri-devel@lists.freedesktop.org On Wed, Aug 07, 2019 at 10:48:56AM +0200, Daniel Vetter wrote: > > other drm drivers how do they guarantee addressability without an > > iommu?) > > We use shmem to get at swappable pages. We generally just assume that > the gpu can get at those pages, but things fall apart in fun ways: > - some setups somehow inject bounce buffers. Some drivers just give > up, others try to allocate a pool of pages with dma_alloc_coherent. > - some devices are misdesigned and can't access as much as the cpu. We > allocate using GFP_DMA32 to fix that. Well, for shmem you can't really call allocators directly, right? One thing I have in my pipeline is a dma_alloc_pages API that allocates pages that are guaranteed to be addressably by the device or otherwise fail. But that doesn't really help with the shmem fs. > Also modern gpu apis pretty much assume you can malloc() and then use > that directly with the gpu. Which is fine as long as the GPU itself supports full 64-bit addressing (or always sits behind an iommu), and the platform doesn't impose addressing limit, which unfortunately some that are shipped right now still do :( But userspace malloc really means dma_map_* anyway, so not really relevant for memory allocations.