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From: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Michel Thierry <michel.thierry@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/i915/tgl: Introduce initial Tigerlake Workarounds
Date: Mon, 12 Aug 2019 15:29:49 -0700	[thread overview]
Message-ID: <20190812222949.GB16513@InViCtUs> (raw)
In-Reply-To: <20190726000226.26914-2-lucas.demarchi@intel.com>

On Thu, Jul 25, 2019 at 05:02:24PM -0700, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Inherit workarounds from previous platforms that are still valid for
> Tigerlake.
> 
>   WaPipelineFlushCoherentLines:tgl (changed register but has same name)
>   WaSendPushConstantsFromMMIO:tgl
>   WaAllowUMDToModifySamplerMode:tgl
>   WaRsForcewakeAddDelayForAck:tgl
> 
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c         |  2 ++
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h             |  3 ++
>  drivers/gpu/drm/i915/intel_pm.c             |  4 ++-
>  drivers/gpu/drm/i915/intel_uncore.c         |  2 +-
>  5 files changed, 46 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 884dfc1cb033..893c58df8be0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2069,6 +2069,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>  		return 0;
>  
>  	switch (INTEL_GEN(engine->i915)) {
> +	case 12:
> +		return 0;
>  	case 11:
>  		return 0;
>  	case 10:
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 704ace01e7f5..a6eb9c6e87ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -569,6 +569,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  			  GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
>  }
>  
> +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> +				     struct i915_wa_list *wal)
> +{
> +}
> +
>  static void
>  __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>  			   struct i915_wa_list *wal,
> @@ -581,7 +586,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>  
>  	wa_init_start(wal, name, engine->name);
>  
> -	if (IS_GEN(i915, 11))
> +	if (IS_GEN(i915, 12))
> +		tgl_ctx_workarounds_init(engine, wal);
> +	else if (IS_GEN(i915, 11))
>  		icl_ctx_workarounds_init(engine, wal);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_ctx_workarounds_init(engine, wal);
> @@ -890,10 +897,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  		    GAMT_CHKN_DISABLE_L3_COH_PIPE);
>  }
>  
> +static void
> +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> +}
> +
>  static void
>  gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  {
> -	if (IS_GEN(i915, 11))
> +	if (IS_GEN(i915, 12))
> +		tgl_gt_workarounds_init(i915, wal);
> +	else if (IS_GEN(i915, 11))
>  		icl_gt_workarounds_init(i915, wal);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_gt_workarounds_init(i915, wal);
> @@ -1183,6 +1197,17 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>  	}
>  }
>  
> +static void tgl_whitelist_build(struct intel_engine_cs *engine)
> +{
> +	struct i915_wa_list *w = &engine->whitelist;
> +
> +	/* WaSendPushConstantsFromMMIO:tgl */
> +	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
> +
> +	/* WaAllowUMDToModifySamplerMode:tgl */
> +	whitelist_reg(w, GEN10_SAMPLER_MODE);
> +}
> +
>  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *i915 = engine->i915;
> @@ -1190,7 +1215,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  
>  	wa_init_start(w, "whitelist", engine->name);
>  
> -	if (IS_GEN(i915, 11))
> +	if (IS_GEN(i915, 12))
> +		tgl_whitelist_build(engine);
> +	else if (IS_GEN(i915, 11))
>  		icl_whitelist_build(engine);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_whitelist_build(engine);
> @@ -1240,6 +1267,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  {
>  	struct drm_i915_private *i915 = engine->i915;
>  
> +	if (IS_GEN(i915, 12)) {
> +		/* WaPipelineFlushCoherentLines:tgl */
> +		wa_write_or(wal,
> +			    GEN12_L3SQCREG2,
> +			    GEN12_LQSC_FLUSH_COHERENT_LINES);
> +	}
> +
>  	if (IS_GEN(i915, 11)) {
>  		/* This is not an Wa. Enable for better image quality */
>  		wa_masked_en(wal,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 24f2a52a2b42..54ea250000be 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7729,6 +7729,9 @@ enum {
>  #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
>  #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
>  
> +#define GEN12_L3SQCREG2				_MMIO(0xb104)
> +#define  GEN12_LQSC_FLUSH_COHERENT_LINES	(1 << 24)
> +
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				_MMIO(0x7300)
>  #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 30399b245f07..63aecff195ce 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9608,7 +9608,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>   */
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_GEN(dev_priv, 11))
> +	if (IS_GEN(dev_priv, 12))
> +		dev_priv->display.init_clock_gating = nop_init_clock_gating;
> +	else if (IS_GEN(dev_priv, 11))
>  		dev_priv->display.init_clock_gating = icl_init_clock_gating;
>  	else if (IS_CANNONLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 475ab3d4d91d..cca046ff2e10 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -144,7 +144,7 @@ fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
>  	 * the fallback ack.
>  	 *
>  	 * This workaround is described in HSDES #1604254524 and it's known as:
> -	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
> +	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl,tgl
>  	 * although the name is a bit misleading.
>  	 */
>  
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2019-08-12 22:28 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-07-26  0:02 [PATCH 0/3] Tiger Lake: add workarounds Lucas De Marchi
2019-07-26  0:02 ` [PATCH 1/3] drm/i915/tgl: Introduce initial Tigerlake Workarounds Lucas De Marchi
2019-08-12 22:29   ` Radhakrishna Sripada [this message]
2019-08-13 18:07   ` Radhakrishna Sripada
2019-08-16  2:47     ` Lucas De Marchi
2019-07-26  0:02 ` [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607 Lucas De Marchi
2019-07-26  0:10   ` Chris Wilson
2019-07-26 13:15     ` Tvrtko Ursulin
2019-07-26 13:20       ` Chris Wilson
2019-07-26 13:34         ` Tvrtko Ursulin
2019-07-26 13:55           ` Chris Wilson
2019-07-26  0:02 ` [PATCH 3/3] drm/i915/tgl: Implement Wa_1406941453 Lucas De Marchi
2019-08-12 22:10   ` Radhakrishna Sripada
2019-07-26  2:47 ` ✓ Fi.CI.BAT: success for Tiger Lake: add workarounds Patchwork
2019-07-27  4:36 ` ✓ Fi.CI.IGT: " Patchwork

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