From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58E9FC3A589 for ; Thu, 15 Aug 2019 17:56:04 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D88062083B for ; Thu, 15 Aug 2019 17:56:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D88062083B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 468Yz51hHVzDr6D for ; Fri, 16 Aug 2019 03:56:01 +1000 (AEST) Authentication-Results: lists.ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lst.de (client-ip=213.95.11.211; helo=verein.lst.de; envelope-from=hch@lst.de; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=lst.de Received: from verein.lst.de (verein.lst.de [213.95.11.211]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 468Ywg5nzbzDqRC for ; Fri, 16 Aug 2019 03:53:54 +1000 (AEST) Received: by verein.lst.de (Postfix, from userid 2407) id E3BED68AFE; Thu, 15 Aug 2019 19:53:46 +0200 (CEST) Date: Thu, 15 Aug 2019 19:53:46 +0200 From: Christoph Hellwig To: Rob Clark Subject: Re: [PATCH 0/6] drm+dma: cache support for arm, etc Message-ID: <20190815175346.GA19839@lst.de> References: <20190814220011.26934-1-robdclark@gmail.com> <20190815065117.GA23761@lst.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kate Stewart , Masayoshi Mizuma , "Maciej W. Rozycki" , Eric Biggers , Catalin Marinas , Imre Deak , dri-devel , Chris Wilson , Masahiro Yamada , Benjamin Gaignard , Mauro Carvalho Chehab , Will Deacon , Christoph Hellwig , Emil Velikov , Deepak Sharma , Paul Burton , Mike Rapoport , Geert Uytterhoeven , "moderated list:ARM64 PORT \(AARCH64 ARCHITECTURE\)" , Daniel Vetter , "open list:MIPS" , Linus Walleij , Robin Murphy , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Joerg Roedel , Arnd Bergmann , Anshuman Khandual , Hauke Mehrtens , Jesper Dangaard Brouer , "Wolfram Sang \(Renesas\)" , "open list:LINUX FOR POWERPC \(32-BIT AND 64-BIT\)" , Alexios Zavras , Russell King , Doug Anderson , Thomas Gleixner , Sean Paul , Allison Randal , Enrico Weigelt , Ard Biesheuvel , Greg Kroah-Hartman , open list , Rob Clark , Souptick Joarder , Andrew Morton , "open list:DRM DRIVER FOR MSM ADRENO GPU" , christian.koenig@amd.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On Thu, Aug 15, 2019 at 06:54:39AM -0700, Rob Clark wrote: > On Wed, Aug 14, 2019 at 11:51 PM Christoph Hellwig wrote: > > > > As said before I don't think these low-level helpers are the > > right API to export, but even if they did you'd just cover a tiny > > subset of the architectures. > > Are you thinking instead something like: > > void dma_sync_sg_for_{cpu,device}(struct device *dev, struct scatterlist *sgl, > int nents, enum dma_data_direction dir) > { > for_each_sg(sgl, sg, nents, i) { > arch_sync_dma_for_..(dev, sg_phys(sg), sg->length, dir); > } > } > EXPORT_SYMBOL_GPL(dma_sync_sg_for_..) > > or did you have something else in mind? No. We really need an interface thay says please give me uncached memory (for some definition of uncached that includes that grapics drivers call write combine), and then let the architecture do the right thing. Basically dma_alloc_coherent with DMA_ATTR_NO_KERNEL_MAPPING is superficially close to what you want, except that the way the drm drivers work you can't actually use it. The reason for that is if we can we really need to not create another uncachable alias, but instead change the page attributes in place. On x86 we can and must do that for example, and based on the conversation with Will arm64 could do that fairly easily. arm32 can right now only do that for CMA, though. The big question is what API do we want. I had a pretty similar discussion with Christian on doing such an allocation for amdgpu, where the device normally is cache coherent, but they actually want to turn it into non-coherent by using PCIe unsnooped transactions. Here is my high level plan, which still has a few lose end: (1) provide a new API: struct page *dma_alloc_pages(struct device *dev, unsigned nr_pages, gfp_t gfp, unsigned long flags); void dma_free_pages(struct device *dev, unsigned nr_pages, unsigned long flags); These give you back page backed memory that is guaranteed to be addressable by the device (no swiotlb or similar). The memory can then be mapped using dma_map*, including unmap and dma_sync to bounce ownership around. This is the replacement for the current dma_alloc_attrs with DMA_ATTR_NON_CONSISTENT API, that is rather badly defined. (2) Add support for DMA_ATTR_NO_KERNEL_MAPPING to this new API instead of dma_alloc_attrs. The initial difference with that flag is just that we allow highmem, but in the future we could also unmap this memory from the kernel linear mapping entirely on architectures where we can easily do that. (3) Add a dma_pages_map/dma_pages_unmap or similar API that allows you to get a kernel mapping for parts or all of a DMA_ATTR_NO_KERNEL_MAPPING allocation. This is to replace things like your open-coded vmap in msm (or similarly elsewhere in dma-buf providers). (4) Add support for a DMA_ATTR_UNCACHABLE flags (or similar) to the new API, that maps the pages as uncachable iff they have a kernel mapping, including invalidating the caches at time of this page attribute change (or creation of a new mapping). This API will fail if the architecture does not allow in-place remapping. Note that for arm32 we could always dip into the CMA pool if one is present to not fail. We'll also need some helper to map from the DMA_ATTR_* flags to a pgprot for mapping the page to userspace. There is also a few other weird bits here, e.g. on architectures like mips that use an uncached segment we'll have to fail use with the plain DMA_ATTR_UNCACHABLE flag, but it could be supported with DMA_ATTR_UNCACHABLE | DMA_ATTR_NO_KERNEL_MAPPING. I was hoping to get most of this done for this merge window, but I'm probably lucky if I get at least parts done. Too much distraction. > Hmm, not entirely sure why.. you should be on the cc list for each > individual patch. They finally made it, although even with the delay they only ended up in the spam mailbox. I still can't see them on the various mailing lists. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 538F3C3A589 for ; Thu, 15 Aug 2019 17:54:02 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 26CC12083B for ; Thu, 15 Aug 2019 17:54:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="J489TKXs" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 26CC12083B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=lst.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=gllr+TGtLgNLQ47iNeutzwgg862Rgn2WGXfkjoxtdeg=; b=J489TKXsuyRGOY rOx4d9r9sQGp7If5GzaEvx8Hs3/De5pL0OzNtnoskvKiQ4SBJS87kP8CbhqqC9c0bIhwq8JfTUy3l DG53doS5zo/avb/gffn8164A/i3l132M8as//o+Fpbvi5C8LCOUpL60mMWpgfFlLvnN5wFwrZTMEr DNNzOShqetQ+pTm1918SgqoyF30RgIJHFgR0f8o9IhUI5v4LJNLIUDLlIaU/jSoTnjrLZ63EwCD9z BBjokXqW3QDJQr1uz48P4EuyEXdIThtyAzBsnu7mYbQjiC2MK25Ki/F95oDmQtkMtmNTNTP+JqtYW 34ae8FuIFJ5IoRYAU5Iw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1hyJwm-0003bd-2l; Thu, 15 Aug 2019 17:54:00 +0000 Received: from verein.lst.de ([213.95.11.211]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1hyJwg-0003b6-QR for linux-arm-kernel@lists.infradead.org; Thu, 15 Aug 2019 17:53:58 +0000 Received: by verein.lst.de (Postfix, from userid 2407) id E3BED68AFE; Thu, 15 Aug 2019 19:53:46 +0200 (CEST) Date: Thu, 15 Aug 2019 19:53:46 +0200 From: Christoph Hellwig To: Rob Clark Subject: Re: [PATCH 0/6] drm+dma: cache support for arm, etc Message-ID: <20190815175346.GA19839@lst.de> References: <20190814220011.26934-1-robdclark@gmail.com> <20190815065117.GA23761@lst.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17 (2007-11-01) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190815_105355_160591_D733D074 X-CRM114-Status: GOOD ( 25.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kate Stewart , Masayoshi Mizuma , "Maciej W. Rozycki" , Eric Biggers , Catalin Marinas , Imre Deak , dri-devel , Chris Wilson , Masahiro Yamada , Benjamin Gaignard , Mauro Carvalho Chehab , Will Deacon , Christoph Hellwig , Emil Velikov , Deepak Sharma , Michael Ellerman , Paul Burton , Mike Rapoport , Geert Uytterhoeven , "moderated list:ARM64 PORT \(AARCH64 ARCHITECTURE\)" , Daniel Vetter , "open list:MIPS" , Linus Walleij , Robin Murphy , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Joerg Roedel , Arnd Bergmann , Anshuman Khandual , Hauke Mehrtens , Jesper Dangaard Brouer , "Wolfram Sang \(Renesas\)" , "open list:LINUX FOR POWERPC \(32-BIT AND 64-BIT\)" , Alexios Zavras , Russell King , Doug Anderson , Thomas Gleixner , Sean Paul , Allison Randal , Christophe Leroy , Enrico Weigelt , Ard Biesheuvel , Greg Kroah-Hartman , open list , Rob Clark , Souptick Joarder , Andrew Morton , "open list:DRM DRIVER FOR MSM ADRENO GPU" , christian.koenig@amd.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Aug 15, 2019 at 06:54:39AM -0700, Rob Clark wrote: > On Wed, Aug 14, 2019 at 11:51 PM Christoph Hellwig wrote: > > > > As said before I don't think these low-level helpers are the > > right API to export, but even if they did you'd just cover a tiny > > subset of the architectures. > > Are you thinking instead something like: > > void dma_sync_sg_for_{cpu,device}(struct device *dev, struct scatterlist *sgl, > int nents, enum dma_data_direction dir) > { > for_each_sg(sgl, sg, nents, i) { > arch_sync_dma_for_..(dev, sg_phys(sg), sg->length, dir); > } > } > EXPORT_SYMBOL_GPL(dma_sync_sg_for_..) > > or did you have something else in mind? No. We really need an interface thay says please give me uncached memory (for some definition of uncached that includes that grapics drivers call write combine), and then let the architecture do the right thing. Basically dma_alloc_coherent with DMA_ATTR_NO_KERNEL_MAPPING is superficially close to what you want, except that the way the drm drivers work you can't actually use it. The reason for that is if we can we really need to not create another uncachable alias, but instead change the page attributes in place. On x86 we can and must do that for example, and based on the conversation with Will arm64 could do that fairly easily. arm32 can right now only do that for CMA, though. The big question is what API do we want. I had a pretty similar discussion with Christian on doing such an allocation for amdgpu, where the device normally is cache coherent, but they actually want to turn it into non-coherent by using PCIe unsnooped transactions. Here is my high level plan, which still has a few lose end: (1) provide a new API: struct page *dma_alloc_pages(struct device *dev, unsigned nr_pages, gfp_t gfp, unsigned long flags); void dma_free_pages(struct device *dev, unsigned nr_pages, unsigned long flags); These give you back page backed memory that is guaranteed to be addressable by the device (no swiotlb or similar). The memory can then be mapped using dma_map*, including unmap and dma_sync to bounce ownership around. This is the replacement for the current dma_alloc_attrs with DMA_ATTR_NON_CONSISTENT API, that is rather badly defined. (2) Add support for DMA_ATTR_NO_KERNEL_MAPPING to this new API instead of dma_alloc_attrs. The initial difference with that flag is just that we allow highmem, but in the future we could also unmap this memory from the kernel linear mapping entirely on architectures where we can easily do that. (3) Add a dma_pages_map/dma_pages_unmap or similar API that allows you to get a kernel mapping for parts or all of a DMA_ATTR_NO_KERNEL_MAPPING allocation. This is to replace things like your open-coded vmap in msm (or similarly elsewhere in dma-buf providers). (4) Add support for a DMA_ATTR_UNCACHABLE flags (or similar) to the new API, that maps the pages as uncachable iff they have a kernel mapping, including invalidating the caches at time of this page attribute change (or creation of a new mapping). This API will fail if the architecture does not allow in-place remapping. Note that for arm32 we could always dip into the CMA pool if one is present to not fail. We'll also need some helper to map from the DMA_ATTR_* flags to a pgprot for mapping the page to userspace. There is also a few other weird bits here, e.g. on architectures like mips that use an uncached segment we'll have to fail use with the plain DMA_ATTR_UNCACHABLE flag, but it could be supported with DMA_ATTR_UNCACHABLE | DMA_ATTR_NO_KERNEL_MAPPING. I was hoping to get most of this done for this merge window, but I'm probably lucky if I get at least parts done. Too much distraction. > Hmm, not entirely sure why.. you should be on the cc list for each > individual patch. They finally made it, although even with the delay they only ended up in the spam mailbox. I still can't see them on the various mailing lists. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: Re: [PATCH 0/6] drm+dma: cache support for arm, etc Date: Thu, 15 Aug 2019 19:53:46 +0200 Message-ID: <20190815175346.GA19839@lst.de> References: <20190814220011.26934-1-robdclark@gmail.com> <20190815065117.GA23761@lst.de> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: freedreno-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "Freedreno" To: Rob Clark Cc: Kate Stewart , Masayoshi Mizuma , "Maciej W. Rozycki" , Eric Biggers , Catalin Marinas , Imre Deak , dri-devel , Chris Wilson , Masahiro Yamada , Benjamin Gaignard , Mauro Carvalho Chehab , Will Deacon , Christoph Hellwig , Emil Velikov , Deepak Sharma , Michael Ellerman , Paul Burton , Mike Rapoport , Geert Uytterhoeven , "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , Daniel List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCBBdWcgMTUsIDIwMTkgYXQgMDY6NTQ6MzlBTSAtMDcwMCwgUm9iIENsYXJrIHdyb3Rl Ogo+IE9uIFdlZCwgQXVnIDE0LCAyMDE5IGF0IDExOjUxIFBNIENocmlzdG9waCBIZWxsd2lnIDxo Y2hAbHN0LmRlPiB3cm90ZToKPiA+Cj4gPiBBcyBzYWlkIGJlZm9yZSBJIGRvbid0IHRoaW5rIHRo ZXNlIGxvdy1sZXZlbCBoZWxwZXJzIGFyZSB0aGUKPiA+IHJpZ2h0IEFQSSB0byBleHBvcnQsIGJ1 dCBldmVuIGlmIHRoZXkgZGlkIHlvdSdkIGp1c3QgY292ZXIgYSB0aW55Cj4gPiBzdWJzZXQgb2Yg dGhlIGFyY2hpdGVjdHVyZXMuCj4gCj4gQXJlIHlvdSB0aGlua2luZyBpbnN0ZWFkIHNvbWV0aGlu ZyBsaWtlOgo+IAo+IHZvaWQgZG1hX3N5bmNfc2dfZm9yX3tjcHUsZGV2aWNlfShzdHJ1Y3QgZGV2 aWNlICpkZXYsIHN0cnVjdCBzY2F0dGVybGlzdCAqc2dsLAo+ICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICBpbnQgbmVudHMsIGVudW0gZG1hX2RhdGFfZGlyZWN0aW9uIGRpcikKPiB7 Cj4gICAgIGZvcl9lYWNoX3NnKHNnbCwgc2csIG5lbnRzLCBpKSB7Cj4gICAgICAgICBhcmNoX3N5 bmNfZG1hX2Zvcl8uLihkZXYsIHNnX3BoeXMoc2cpLCBzZy0+bGVuZ3RoLCBkaXIpOwo+ICAgICB9 Cj4gfQo+IEVYUE9SVF9TWU1CT0xfR1BMKGRtYV9zeW5jX3NnX2Zvcl8uLikKPiAKPiBvciBkaWQg eW91IGhhdmUgc29tZXRoaW5nIGVsc2UgaW4gbWluZD8KCk5vLiAgV2UgcmVhbGx5IG5lZWQgYW4g aW50ZXJmYWNlIHRoYXkgc2F5cyBwbGVhc2UgZ2l2ZSBtZSB1bmNhY2hlZAptZW1vcnkgKGZvciBz b21lIGRlZmluaXRpb24gb2YgdW5jYWNoZWQgdGhhdCBpbmNsdWRlcyB0aGF0IGdyYXBpY3MKZHJp dmVycyBjYWxsIHdyaXRlIGNvbWJpbmUpLCBhbmQgdGhlbiBsZXQgdGhlIGFyY2hpdGVjdHVyZSBk byB0aGUgcmlnaHQKdGhpbmcuICBCYXNpY2FsbHkgZG1hX2FsbG9jX2NvaGVyZW50IHdpdGggRE1B X0FUVFJfTk9fS0VSTkVMX01BUFBJTkcKaXMgc3VwZXJmaWNpYWxseSBjbG9zZSB0byB3aGF0IHlv dSB3YW50LCBleGNlcHQgdGhhdCB0aGUgd2F5IHRoZSBkcm0KZHJpdmVycyB3b3JrIHlvdSBjYW4n dCBhY3R1YWxseSB1c2UgaXQuCgpUaGUgcmVhc29uIGZvciB0aGF0IGlzIGlmIHdlIGNhbiB3ZSBy ZWFsbHkgbmVlZCB0byBub3QgY3JlYXRlIGFub3RoZXIKdW5jYWNoYWJsZSBhbGlhcywgYnV0IGlu c3RlYWQgY2hhbmdlIHRoZSBwYWdlIGF0dHJpYnV0ZXMgaW4gcGxhY2UuCk9uIHg4NiB3ZSBjYW4g YW5kIG11c3QgZG8gdGhhdCBmb3IgZXhhbXBsZSwgYW5kIGJhc2VkIG9uIHRoZQpjb252ZXJzYXRp b24gd2l0aCBXaWxsIGFybTY0IGNvdWxkIGRvIHRoYXQgZmFpcmx5IGVhc2lseS4gIGFybTMyIGNh bgpyaWdodCBub3cgb25seSBkbyB0aGF0IGZvciBDTUEsIHRob3VnaC4KClRoZSBiaWcgcXVlc3Rp b24gaXMgd2hhdCBBUEkgZG8gd2Ugd2FudC4gIEkgaGFkIGEgcHJldHR5IHNpbWlsYXIKZGlzY3Vz c2lvbiB3aXRoIENocmlzdGlhbiBvbiBkb2luZyBzdWNoIGFuIGFsbG9jYXRpb24gZm9yIGFtZGdw dSwKd2hlcmUgdGhlIGRldmljZSBub3JtYWxseSBpcyBjYWNoZSBjb2hlcmVudCwgYnV0IHRoZXkg YWN0dWFsbHkgd2FudAp0byB0dXJuIGl0IGludG8gbm9uLWNvaGVyZW50IGJ5IHVzaW5nIFBDSWUg dW5zbm9vcGVkIHRyYW5zYWN0aW9ucy4KCkhlcmUgaXMgbXkgaGlnaCBsZXZlbCBwbGFuLCB3aGlj aCBzdGlsbCBoYXMgYSBmZXcgbG9zZSBlbmQ6CgogKDEpIHByb3ZpZGUgYSBuZXcgQVBJOgoKCXN0 cnVjdCBwYWdlICpkbWFfYWxsb2NfcGFnZXMoc3RydWN0IGRldmljZSAqZGV2LCB1bnNpZ25lZCBu cl9wYWdlcywKCQkJZ2ZwX3QgZ2ZwLCB1bnNpZ25lZCBsb25nIGZsYWdzKTsKCXZvaWQgZG1hX2Zy ZWVfcGFnZXMoc3RydWN0IGRldmljZSAqZGV2LCB1bnNpZ25lZCBucl9wYWdlcywKCQkJdW5zaWdu ZWQgbG9uZyBmbGFncyk7CgogICAgIFRoZXNlIGdpdmUgeW91IGJhY2sgcGFnZSBiYWNrZWQgbWVt b3J5IHRoYXQgaXMgZ3VhcmFudGVlZCB0byBiZQogICAgIGFkZHJlc3NhYmxlIGJ5IHRoZSBkZXZp Y2UgKG5vIHN3aW90bGIgb3Igc2ltaWxhcikuICBUaGUgbWVtb3J5IGNhbgogICAgIHRoZW4gYmUg bWFwcGVkIHVzaW5nIGRtYV9tYXAqLCBpbmNsdWRpbmcgdW5tYXAgYW5kIGRtYV9zeW5jIHRvCiAg ICAgYm91bmNlIG93bmVyc2hpcCBhcm91bmQuICBUaGlzIGlzIHRoZSByZXBsYWNlbWVudCBmb3Ig dGhlIGN1cnJlbnQKICAgICBkbWFfYWxsb2NfYXR0cnMgd2l0aCBETUFfQVRUUl9OT05fQ09OU0lT VEVOVCBBUEksIHRoYXQgaXMgcmF0aGVyCiAgICAgYmFkbHkgZGVmaW5lZC4KCiAoMikgQWRkIHN1 cHBvcnQgZm9yIERNQV9BVFRSX05PX0tFUk5FTF9NQVBQSU5HIHRvIHRoaXMgbmV3IEFQSSBpbnN0 ZWFkCiAgICAgb2YgZG1hX2FsbG9jX2F0dHJzLiAgVGhlIGluaXRpYWwgZGlmZmVyZW5jZSB3aXRo IHRoYXQgZmxhZyBpcyBqdXN0CiAgICAgdGhhdCB3ZSBhbGxvdyBoaWdobWVtLCBidXQgaW4gdGhl IGZ1dHVyZSB3ZSBjb3VsZCBhbHNvIHVubWFwIHRoaXMKICAgICBtZW1vcnkgZnJvbSB0aGUga2Vy bmVsIGxpbmVhciBtYXBwaW5nIGVudGlyZWx5IG9uIGFyY2hpdGVjdHVyZXMKICAgICB3aGVyZSB3 ZSBjYW4gZWFzaWx5IGRvIHRoYXQuCgogKDMpIEFkZCBhIGRtYV9wYWdlc19tYXAvZG1hX3BhZ2Vz X3VubWFwIG9yIHNpbWlsYXIgQVBJIHRoYXQgYWxsb3dzIHlvdQogICAgIHRvIGdldCBhIGtlcm5l bCBtYXBwaW5nIGZvciBwYXJ0cyBvciBhbGwgb2YgYQogICAgIERNQV9BVFRSX05PX0tFUk5FTF9N QVBQSU5HIGFsbG9jYXRpb24uICBUaGlzIGlzIHRvIHJlcGxhY2UgdGhpbmdzCiAgICAgbGlrZSB5 b3VyIG9wZW4tY29kZWQgdm1hcCBpbiBtc20gKG9yIHNpbWlsYXJseSBlbHNld2hlcmUgaW4gZG1h LWJ1ZgogICAgIHByb3ZpZGVycykuCgogKDQpIEFkZCBzdXBwb3J0IGZvciBhIERNQV9BVFRSX1VO Q0FDSEFCTEUgZmxhZ3MgKG9yIHNpbWlsYXIpIHRvIHRoZSBuZXcKICAgICBBUEksIHRoYXQgbWFw cyB0aGUgcGFnZXMgYXMgdW5jYWNoYWJsZSBpZmYgdGhleSBoYXZlIGEga2VybmVsCiAgICAgbWFw cGluZywgaW5jbHVkaW5nIGludmFsaWRhdGluZyB0aGUgY2FjaGVzIGF0IHRpbWUgb2YgdGhpcyBw YWdlCiAgICAgYXR0cmlidXRlIGNoYW5nZSAob3IgY3JlYXRpb24gb2YgYSBuZXcgbWFwcGluZyku ICBUaGlzIEFQSSB3aWxsIGZhaWwKICAgICBpZiB0aGUgYXJjaGl0ZWN0dXJlIGRvZXMgbm90IGFs bG93IGluLXBsYWNlIHJlbWFwcGluZy4gIE5vdGUgdGhhdCBmb3IKICAgICBhcm0zMiB3ZSBjb3Vs ZCBhbHdheXMgZGlwIGludG8gdGhlIENNQSBwb29sIGlmIG9uZSBpcyBwcmVzZW50IHRvIG5vdAog ICAgIGZhaWwuICBXZSdsbCBhbHNvIG5lZWQgc29tZSBoZWxwZXIgdG8gbWFwIGZyb20gdGhlIERN QV9BVFRSXyogZmxhZ3MKICAgICB0byBhIHBncHJvdCBmb3IgbWFwcGluZyB0aGUgcGFnZSB0byB1 c2Vyc3BhY2UuICBUaGVyZSBpcyBhbHNvIGEgZmV3CiAgICAgb3RoZXIgd2VpcmQgYml0cyBoZXJl LCBlLmcuIG9uIGFyY2hpdGVjdHVyZXMgbGlrZSBtaXBzIHRoYXQgdXNlIGFuCiAgICAgdW5jYWNo ZWQgc2VnbWVudCB3ZSdsbCBoYXZlIHRvIGZhaWwgdXNlIHdpdGggdGhlIHBsYWluCiAgICAgRE1B X0FUVFJfVU5DQUNIQUJMRSBmbGFnLCBidXQgaXQgY291bGQgYmUgc3VwcG9ydGVkIHdpdGgKICAg ICBETUFfQVRUUl9VTkNBQ0hBQkxFIHwgRE1BX0FUVFJfTk9fS0VSTkVMX01BUFBJTkcuCgpJIHdh cyBob3BpbmcgdG8gZ2V0IG1vc3Qgb2YgdGhpcyBkb25lIGZvciB0aGlzIG1lcmdlIHdpbmRvdywg YnV0IEknbQpwcm9iYWJseSBsdWNreSBpZiBJIGdldCBhdCBsZWFzdCBwYXJ0cyBkb25lLiAgVG9v IG11Y2ggZGlzdHJhY3Rpb24uCgo+IEhtbSwgbm90IGVudGlyZWx5IHN1cmUgd2h5Li4geW91IHNo b3VsZCBiZSBvbiB0aGUgY2MgbGlzdCBmb3IgZWFjaAo+IGluZGl2aWR1YWwgcGF0Y2guCgpUaGV5 IGZpbmFsbHkgbWFkZSBpdCwgYWx0aG91Z2ggZXZlbiB3aXRoIHRoZSBkZWxheSB0aGV5IG9ubHkg ZW5kZWQgdXAKaW4gdGhlIHNwYW0gbWFpbGJveC4gIEkgc3RpbGwgY2FuJ3Qgc2VlIHRoZW0gb24g dGhlIHZhcmlvdXMgbWFpbGluZwpsaXN0cy4KX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX18KRnJlZWRyZW5vIG1haWxpbmcgbGlzdApGcmVlZHJlbm9AbGlzdHMu ZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlz dGluZm8vZnJlZWRyZW5v