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From: "hch@lst.de" <hch@lst.de>
To: Atish Patra <Atish.Patra@wdc.com>
Cc: Damien Le Moal <Damien.LeMoal@wdc.com>,
	"palmer@sifive.com" <palmer@sifive.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>, "hch@lst.de" <hch@lst.de>
Subject: Re: [PATCH 08/15] riscv: provide native clint access for M-mode
Date: Wed, 21 Aug 2019 02:42:41 +0200	[thread overview]
Message-ID: <20190821004241.GA20250@lst.de> (raw)
In-Reply-To: <fa0570285684e03587ee8f09b86f0d058d757c55.camel@wdc.com>

On Wed, Aug 21, 2019 at 12:24:31AM +0000, Atish Patra wrote:
> > +static inline void clint_set_timer(unsigned long delta)
> > +{
> > +	writeq_relaxed(clint_read_timer() + delta,
> > +		clint_time_cmp +
> > cpuid_to_hartid_map(smp_processor_id()));'
> 
> This is not compatible with 32 bit mode. IIRC, timecmp is a 64 bit on
> RV32 as well. Here is the implementation in OpenSBI.

writeq alwasy writes 64-bit anyway, but the deltas is just 32-bit
per the Linux clocksource API.

> > +static inline cycles_t get_cycles(void)
> > +{
> > +#ifdef CONFIG_64BIT
> > +	return readq_relaxed(clint_time_val);
> > +#else
> > +	return readl_relaxed(clint_time_val);
> > +#endif
> 
> Same comment as above. Both RV32 & RV64 bit have 64 bit have 64 bit
> precission for timer val. You have to read 32 bits at a time and "or"
> them to get 64 bit value. Here is the implementation from OpenSBI

But the Linux API is only going to read 32-bits of that, same as
for the rdtime pseudo-instruction used by the current SBI-based code.

Note that I've reworked this area a bit for v4, which I'm going to
send out soon, including cleanups to the existing code to make a few
of these things more obvious:

http://git.infradead.org/users/hch/riscv.git/shortlog/refs/heads/riscv-nommu.4

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WARNING: multiple messages have this Message-ID (diff)
From: "hch@lst.de" <hch@lst.de>
To: Atish Patra <Atish.Patra@wdc.com>
Cc: "hch@lst.de" <hch@lst.de>,
	"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
	"palmer@sifive.com" <palmer@sifive.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	Damien Le Moal <Damien.LeMoal@wdc.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 08/15] riscv: provide native clint access for M-mode
Date: Wed, 21 Aug 2019 02:42:41 +0200	[thread overview]
Message-ID: <20190821004241.GA20250@lst.de> (raw)
In-Reply-To: <fa0570285684e03587ee8f09b86f0d058d757c55.camel@wdc.com>

On Wed, Aug 21, 2019 at 12:24:31AM +0000, Atish Patra wrote:
> > +static inline void clint_set_timer(unsigned long delta)
> > +{
> > +	writeq_relaxed(clint_read_timer() + delta,
> > +		clint_time_cmp +
> > cpuid_to_hartid_map(smp_processor_id()));'
> 
> This is not compatible with 32 bit mode. IIRC, timecmp is a 64 bit on
> RV32 as well. Here is the implementation in OpenSBI.

writeq alwasy writes 64-bit anyway, but the deltas is just 32-bit
per the Linux clocksource API.

> > +static inline cycles_t get_cycles(void)
> > +{
> > +#ifdef CONFIG_64BIT
> > +	return readq_relaxed(clint_time_val);
> > +#else
> > +	return readl_relaxed(clint_time_val);
> > +#endif
> 
> Same comment as above. Both RV32 & RV64 bit have 64 bit have 64 bit
> precission for timer val. You have to read 32 bits at a time and "or"
> them to get 64 bit value. Here is the implementation from OpenSBI

But the Linux API is only going to read 32-bits of that, same as
for the rdtime pseudo-instruction used by the current SBI-based code.

Note that I've reworked this area a bit for v4, which I'm going to
send out soon, including cleanups to the existing code to make a few
of these things more obvious:

http://git.infradead.org/users/hch/riscv.git/shortlog/refs/heads/riscv-nommu.4

  reply	other threads:[~2019-08-21  0:42 UTC|newest]

Thread overview: 90+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-13 15:47 RISC-V nommu support v3 Christoph Hellwig
2019-08-13 15:47 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-13 17:44   ` Paul Walmsley
2019-08-13 17:44     ` Paul Walmsley
2019-08-14  9:06     ` Marc Zyngier
2019-08-14  9:06       ` Marc Zyngier
2019-08-13 15:47 ` [PATCH 02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-13 16:36   ` Paul Walmsley
2019-08-13 16:36     ` Paul Walmsley
2019-08-13 16:42     ` Christoph Hellwig
2019-08-13 16:42       ` Christoph Hellwig
2019-08-13 16:51       ` Paul Walmsley
2019-08-13 16:51         ` Paul Walmsley
2019-08-13 19:44   ` Paul Walmsley
2019-08-13 19:44     ` Paul Walmsley
2019-08-13 15:47 ` [PATCH 03/15] riscv: refactor the IPI code Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-14  4:41   ` Paul Walmsley
2019-08-14  4:41     ` Paul Walmsley
2019-08-19 10:18     ` Christoph Hellwig
2019-08-19 10:18       ` Christoph Hellwig
2019-09-01  8:03     ` Christoph Hellwig
2019-09-01  8:03       ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 04/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 05/15] riscv: improve the default power off implementation Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 06/15] riscv: provide a flat entry loader Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 07/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 08/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-13 16:29   ` Mark Rutland
2019-08-13 16:29     ` Mark Rutland
2019-08-19 10:16     ` Christoph Hellwig
2019-08-19 10:16       ` Christoph Hellwig
2019-08-27 23:37       ` Palmer Dabbelt
2019-08-27 23:37         ` Palmer Dabbelt
2019-08-28  6:11         ` Christoph Hellwig
2019-08-28  6:11           ` Christoph Hellwig
2019-09-03 18:48           ` Palmer Dabbelt
2019-09-03 18:48             ` Palmer Dabbelt
2019-09-04  2:05             ` Alan Kao
2019-09-04  2:05               ` Alan Kao
2019-08-21  0:24   ` Atish Patra
2019-08-21  0:24     ` Atish Patra
2019-08-21  0:42     ` hch [this message]
2019-08-21  0:42       ` hch
2019-08-13 15:47 ` [PATCH 09/15] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-20 21:04   ` Atish Patra
2019-08-20 21:04     ` Atish Patra
2019-08-13 15:47 ` [PATCH 10/15] riscv: poison SBI calls " Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-20 21:05   ` Atish Patra
2019-08-20 21:05     ` Atish Patra
2019-08-13 15:47 ` [PATCH 11/15] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 12/15] riscv: use the correct interrupt levels " Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-14  1:00   ` Alan Kao
2019-08-14  1:00     ` Alan Kao
2019-08-14  1:07     ` Alan Kao
2019-08-14  1:07       ` Alan Kao
2019-08-14  4:35     ` Christoph Hellwig
2019-08-14  4:35       ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 14/15] riscv: add nommu support Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-08-13 15:47   ` Christoph Hellwig
2019-08-20 21:07   ` Atish Patra
2019-08-20 21:07     ` Atish Patra
2019-08-21  4:14   ` Troy Benjegerdes
2019-08-21  4:14     ` Troy Benjegerdes
2019-08-21  7:12     ` Christoph Hellwig
2019-08-21  7:12       ` Christoph Hellwig
2019-08-21 17:31     ` Atish Patra
2019-08-21 17:31       ` Atish Patra
2019-08-21 17:54       ` Troy Benjegerdes
2019-08-21 17:54         ` Troy Benjegerdes
2019-08-21 23:02         ` Anup Patel
2019-08-21 23:02           ` Anup Patel
2019-08-21 23:32           ` Troy Benjegerdes
2019-08-21 23:32             ` Troy Benjegerdes

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