From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BC3BC3A5A4 for ; Sun, 25 Aug 2019 17:43:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1FE5C2173E for ; Sun, 25 Aug 2019 17:43:58 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=vdorst.com header.i=@vdorst.com header.b="atwT2QMT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728772AbfHYRn5 (ORCPT ); Sun, 25 Aug 2019 13:43:57 -0400 Received: from mx.0dd.nl ([5.2.79.48]:38718 "EHLO mx.0dd.nl" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728584AbfHYRn5 (ORCPT ); Sun, 25 Aug 2019 13:43:57 -0400 Received: from mail.vdorst.com (mail.vdorst.com [IPv6:fd01::250]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.0dd.nl (Postfix) with ESMTPS id 4224B5FD0D; Sun, 25 Aug 2019 19:43:55 +0200 (CEST) Authentication-Results: mx.0dd.nl; dkim=pass (2048-bit key) header.d=vdorst.com header.i=@vdorst.com header.b="atwT2QMT"; dkim-atps=neutral Received: from pc-rene.vdorst.com (pc-rene.vdorst.com [192.168.2.125]) by mail.vdorst.com (Postfix) with ESMTPA id 057331D8E166; Sun, 25 Aug 2019 19:43:55 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.vdorst.com 057331D8E166 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vdorst.com; s=default; t=1566755035; bh=7ebJM33QQ0k5xG40NPef/hKLC+qMN+E9QE4LSvqBjWc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=atwT2QMTxyYUN19XGlgbDkFLFBiYj8ZedhZXSHqJPZb2ihi0R+TXrtrTRXbJUTg8q H12gJrZ1AU9hm3z58r2/5GJbqY3/WJRwzJ1kFRqELQnHHAVTHYVPAEShX8cfqfdWS5 LiCyZdKyo+Sl2CBrStr/9iAxoGu8vg61eEtXA7QQVl5QkIaPejzpyVhknJW1k4wFD6 ByQV33qkdmrLgUTEPGemtDxr2hsrqWwzlsg5DGf76+zIEAtfMPVLTSfMmIa60Az5l1 jnJ3bIAL8GaZxvR0fksdM7K9O7IZMuRZdXeDVHPtEarPcmwmoDYZnbFyDV+09M+DcG 0v4OB4yDpdWyg== From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= To: John Crispin , Sean Wang , Nelson Chang , "David S . Miller" , Matthias Brugger Cc: netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-mips@vger.kernel.org, Russell King , Frank Wunderlich , Stefan Roese , =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= Subject: [PATCH net-next v4 2/3] net: ethernet: mediatek: Re-add support SGMII Date: Sun, 25 Aug 2019 19:43:40 +0200 Message-Id: <20190825174341.20750-3-opensource@vdorst.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190825174341.20750-1-opensource@vdorst.com> References: <20190825174341.20750-1-opensource@vdorst.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org * Re-add SGMII support but now with PHYLINK API support So the SGMII changes are more clear * Move SGMII block setup from mtk_gmac_sgmii_path_setup() to mtk_mac_config() * Merge mtk_setup_hw_path() into mtk_mac_config() * Remove mediatek,physpeed property, fixed-link supports now any speed so speed = <2500>; is now valid with PHYLINK * Demagic SGMII register values * Use phylink state to setup fixed-link mode Signed-off-by: René van Dorst -- v3->v4: * Refactor validate() to incorporate the following items. * Also report 1000baseX_Full for SGMII and GMII modes. Suggested by Russell King * Report both 1000BaseX and 2500BaseX modes in both BaseX mode. As Russsell King explains here: https://lore.kernel.org/netdev/20190824091106.GC13294@shell.armlinux.org.uk/ v2->v3: * Redo validate(), it was totally wrong. Noticed by Russell King. v1->v2: * SGMII port only support SGMII at 1Gbit, 1000BASE-X and 2500BASE-X. Also SGMII mode only does auto-negotiation. * Change validate() to support mt76x8 changes. --- drivers/net/ethernet/mediatek/mtk_eth_path.c | 75 +-------- drivers/net/ethernet/mediatek/mtk_eth_soc.c | 151 ++++++++++++++++--- drivers/net/ethernet/mediatek/mtk_eth_soc.h | 37 ++++- drivers/net/ethernet/mediatek/mtk_sgmii.c | 65 +++++--- 4 files changed, 213 insertions(+), 115 deletions(-) diff --git a/drivers/net/ethernet/mediatek/mtk_eth_path.c b/drivers/net/ethernet/mediatek/mtk_eth_path.c index 28960e4c4e43..ef11cf3d1ccc 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c @@ -239,10 +239,9 @@ static int mtk_eth_mux_setup(struct mtk_eth *eth, int path) return err; } -static int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) +int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) { - unsigned int val = 0; - int sid, err, path; + int err, path; path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII : MTK_ETH_PATH_GMAC2_SGMII; @@ -252,33 +251,10 @@ static int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) if (err) return err; - /* The path GMAC to SGMII will be enabled once the SGMIISYS is being - * setup done. - */ - regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); - - regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, - SYSCFG0_SGMII_MASK, ~(u32)SYSCFG0_SGMII_MASK); - - /* Decide how GMAC and SGMIISYS be mapped */ - sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? 0 : mac_id; - - /* Setup SGMIISYS with the determined property */ - if (MTK_HAS_FLAGS(eth->sgmii->flags[sid], MTK_SGMII_PHYSPEED_AN)) - err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); - else - err = mtk_sgmii_setup_mode_force(eth->sgmii, sid); - - if (err) - return err; - - regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, - SYSCFG0_SGMII_MASK, val); - return 0; } -static int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id) +int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id) { int err, path = 0; @@ -296,7 +272,7 @@ static int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id) return 0; } -static int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id) +int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id) { int err, path; @@ -311,46 +287,3 @@ static int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id) return 0; } -int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode) -{ - int err; - - /* No mux'ing for MT7628/88 */ - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) - return 0; - - switch (phymode) { - case PHY_INTERFACE_MODE_TRGMII: - case PHY_INTERFACE_MODE_RGMII_TXID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_MII: - case PHY_INTERFACE_MODE_REVMII: - case PHY_INTERFACE_MODE_RMII: - if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { - err = mtk_gmac_rgmii_path_setup(eth, mac_id); - if (err) - return err; - } - break; - case PHY_INTERFACE_MODE_SGMII: - if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { - err = mtk_gmac_sgmii_path_setup(eth, mac_id); - if (err) - return err; - } - break; - case PHY_INTERFACE_MODE_GMII: - if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { - err = mtk_gmac_gephy_path_setup(eth, mac_id); - if (err) - return err; - } - break; - default: - break; - } - - return 0; -} diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c index 7d2566dd4ce0..b41884e12434 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c @@ -193,8 +193,8 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode, struct mtk_mac *mac = container_of(config, struct mtk_mac, phylink_config); struct mtk_eth *eth = mac->hw; - u32 mcr_cur, mcr_new; - int val, ge_mode = 0; + u32 mcr_cur, mcr_new, sid; + int val, ge_mode, err; /* MT76x8 has no hardware settings between for the MAC */ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && @@ -208,29 +208,42 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode, MTK_GMAC1_TRGMII)) goto err_phy; /* fall through */ - case PHY_INTERFACE_MODE_GMII: case PHY_INTERFACE_MODE_RGMII_TXID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII: - break; case PHY_INTERFACE_MODE_MII: - ge_mode = 1; - break; case PHY_INTERFACE_MODE_REVMII: - ge_mode = 2; - break; case PHY_INTERFACE_MODE_RMII: - if (mac->id) - goto err_phy; - ge_mode = 3; + if (MTK_HAS_CAPS(eth->soc->caps, MTK_RGMII)) { + err = mtk_gmac_rgmii_path_setup(eth, mac->id); + if (err) + goto init_err; + } + break; + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_SGMII: + if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) { + err = mtk_gmac_sgmii_path_setup(eth, mac->id); + if (err) + goto init_err; + } + break; + case PHY_INTERFACE_MODE_GMII: + if (MTK_HAS_CAPS(eth->soc->caps, MTK_GEPHY)) { + err = mtk_gmac_gephy_path_setup(eth, mac->id); + if (err) + goto init_err; + } break; default: goto err_phy; } /* Setup clock for 1st gmac */ - if (!mac->id && + if (!mac->id && state->interface != PHY_INTERFACE_MODE_SGMII && + !phy_interface_mode_is_8023z(state->interface) && MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII)) { if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII_MT7621_CLK)) { @@ -245,6 +258,23 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode, } } + ge_mode = 0; + switch (state->interface) { + case PHY_INTERFACE_MODE_MII: + ge_mode = 1; + break; + case PHY_INTERFACE_MODE_REVMII: + ge_mode = 2; + break; + case PHY_INTERFACE_MODE_RMII: + if (mac->id) + goto err_phy; + ge_mode = 3; + break; + default: + break; + } + /* put the gmac into the right mode */ regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id); @@ -254,6 +284,40 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode, mac->interface = state->interface; } + /* SGMII */ + if (state->interface == PHY_INTERFACE_MODE_SGMII || + phy_interface_mode_is_8023z(state->interface)) { + /* The path GMAC to SGMII will be enabled once the SGMIISYS is + * being setup done. + */ + regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val); + + regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, + SYSCFG0_SGMII_MASK, + ~(u32)SYSCFG0_SGMII_MASK); + + /* Decide how GMAC and SGMIISYS be mapped */ + sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? + 0 : mac->id; + + /* Setup SGMIISYS with the determined property */ + if (state->interface != PHY_INTERFACE_MODE_SGMII) + err = mtk_sgmii_setup_mode_force(eth->sgmii, sid, + state); + else if (phylink_autoneg_inband(mode)) + err = mtk_sgmii_setup_mode_an(eth->sgmii, sid); + + if (err) + goto init_err; + + regmap_update_bits(eth->ethsys, ETHSYS_SYSCFG0, + SYSCFG0_SGMII_MASK, val); + } else if (phylink_autoneg_inband(mode)) { + dev_err(eth->dev, + "In-band mode not supported in non SGMII mode!\n"); + return; + } + /* Setup gmac */ mcr_cur = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id)); mcr_new = mcr_cur; @@ -264,6 +328,7 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode, MAC_MCR_BACKOFF_EN | MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_LINK; switch (state->speed) { + case SPEED_2500: case SPEED_1000: mcr_new |= MAC_MCR_SPEED_1000; break; @@ -288,6 +353,11 @@ static void mtk_mac_config(struct phylink_config *config, unsigned int mode, err_phy: dev_err(eth->dev, "%s: GMAC%d mode %s not supported!\n", __func__, mac->id, phy_modes(state->interface)); + return; + +init_err: + dev_err(eth->dev, "%s: GMAC%d mode %s err: %d!\n", __func__, + mac->id, phy_modes(state->interface), err); } static int mtk_mac_link_state(struct phylink_config *config, @@ -326,7 +396,10 @@ static int mtk_mac_link_state(struct phylink_config *config, static void mtk_mac_an_restart(struct phylink_config *config) { - /* Do nothing */ + struct mtk_mac *mac = container_of(config, struct mtk_mac, + phylink_config); + + mtk_sgmii_restart_an(mac->hw, mac->id); } static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode, @@ -366,7 +439,10 @@ static void mtk_validate(struct phylink_config *config, !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII) && phy_interface_mode_is_rgmii(state->interface)) && !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && - !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII)) { + !mac->id && state->interface == PHY_INTERFACE_MODE_TRGMII) && + !(MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII) && + (state->interface == PHY_INTERFACE_MODE_SGMII || + phy_interface_mode_is_8023z(state->interface)))) { linkmode_zero(supported); return; } @@ -374,19 +450,53 @@ static void mtk_validate(struct phylink_config *config, phylink_set_port_modes(mask); phylink_set(mask, Autoneg); - if (state->interface == PHY_INTERFACE_MODE_TRGMII) { + switch (state->interface) { + case PHY_INTERFACE_MODE_TRGMII: phylink_set(mask, 1000baseT_Full); - } else { + break; + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + phylink_set(mask, 1000baseX_Full); + phylink_set(mask, 2500baseX_Full); + break; + case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + phylink_set(mask, 1000baseT_Half); + /* fall through */ + case PHY_INTERFACE_MODE_SGMII: + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseX_Full); + /* fall through */ + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_RMII: + case PHY_INTERFACE_MODE_REVMII: + case PHY_INTERFACE_MODE_NA: + default: phylink_set(mask, 10baseT_Half); phylink_set(mask, 10baseT_Full); phylink_set(mask, 100baseT_Half); phylink_set(mask, 100baseT_Full); + break; + } - if (state->interface != PHY_INTERFACE_MODE_MII) { - phylink_set(mask, 1000baseT_Half); + if (state->interface == PHY_INTERFACE_MODE_NA) { + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_SGMII)) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseX_Full); + phylink_set(mask, 2500baseX_Full); + } + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII)) { phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); phylink_set(mask, 1000baseX_Full); } + if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GEPHY)) { + phylink_set(mask, 1000baseT_Full); + phylink_set(mask, 1000baseT_Half); + } } phylink_set(mask, Pause); @@ -394,6 +504,11 @@ static void mtk_validate(struct phylink_config *config, linkmode_and(supported, supported, mask); linkmode_and(state->advertising, state->advertising, mask); + + /* We can only operate at 2500BaseX or 1000BaseX. If requested + * to advertise both, only report advertising at 2500BaseX. + */ + phylink_helper_basex_speed(state); } static const struct phylink_mac_ops mtk_phylink_ops = { diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h index 7f5f541daad7..76bd12cb8150 100644 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h @@ -412,14 +412,38 @@ /* Register to auto-negotiation restart */ #define SGMSYS_PCS_CONTROL_1 0x0 #define SGMII_AN_RESTART BIT(9) +#define SGMII_ISOLATE BIT(10) +#define SGMII_AN_ENABLE BIT(12) +#define SGMII_LINK_STATYS BIT(18) +#define SGMII_AN_ABILITY BIT(19) +#define SGMII_AN_COMPLETE BIT(21) +#define SGMII_PCS_FAULT BIT(23) +#define SGMII_AN_EXPANSION_CLR BIT(30) /* Register to programmable link timer, the unit in 2 * 8ns */ #define SGMSYS_PCS_LINK_TIMER 0x18 #define SGMII_LINK_TIMER_DEFAULT (0x186a0 & GENMASK(19, 0)) /* Register to control remote fault */ -#define SGMSYS_SGMII_MODE 0x20 -#define SGMII_REMOTE_FAULT_DIS BIT(8) +#define SGMSYS_SGMII_MODE 0x20 +#define SGMII_IF_MODE_BIT0 BIT(0) +#define SGMII_SPEED_DUPLEX_AN BIT(1) +#define SGMII_SPEED_10 0x0 +#define SGMII_SPEED_100 BIT(2) +#define SGMII_SPEED_1000 BIT(3) +#define SGMII_DUPLEX_FULL BIT(4) +#define SGMII_IF_MODE_BIT5 BIT(5) +#define SGMII_REMOTE_FAULT_DIS BIT(8) +#define SGMII_CODE_SYNC_SET_VAL BIT(9) +#define SGMII_CODE_SYNC_SET_EN BIT(10) +#define SGMII_SEND_AN_ERROR_EN BIT(11) +#define SGMII_IF_MODE_MASK GENMASK(5, 1) + +/* Register to set SGMII speed, ANA RG_ Control Signals III*/ +#define SGMSYS_ANA_RG_CS3 0x2028 +#define RG_PHY_SPEED_MASK (BIT(2) | BIT(3)) +#define RG_PHY_SPEED_1_25G 0x0 +#define RG_PHY_SPEED_3_125G BIT(2) /* Register to power up QPHY */ #define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8 @@ -897,7 +921,12 @@ u32 mtk_r32(struct mtk_eth *eth, unsigned reg); int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np, u32 ana_rgc3); int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id); -int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id); -int mtk_setup_hw_path(struct mtk_eth *eth, int mac_id, int phymode); +int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, + const struct phylink_link_state *state); +void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id); + +int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); +int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id); +int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id); #endif /* MTK_ETH_H */ diff --git a/drivers/net/ethernet/mediatek/mtk_sgmii.c b/drivers/net/ethernet/mediatek/mtk_sgmii.c index ff509d42d818..4db27dfc7ec1 100644 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c @@ -16,8 +16,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3) { struct device_node *np; - const char *str; - int i, err; + int i; ss->ana_rgc3 = ana_rgc3; @@ -29,19 +28,6 @@ int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3) ss->regmap[i] = syscon_node_to_regmap(np); if (IS_ERR(ss->regmap[i])) return PTR_ERR(ss->regmap[i]); - - err = of_property_read_string(np, "mediatek,physpeed", &str); - if (err) - return err; - - if (!strcmp(str, "2500")) - ss->flags[i] |= MTK_SGMII_PHYSPEED_2500; - else if (!strcmp(str, "1000")) - ss->flags[i] |= MTK_SGMII_PHYSPEED_1000; - else if (!strcmp(str, "auto")) - ss->flags[i] |= MTK_SGMII_PHYSPEED_AN; - else - return -EINVAL; } return 0; @@ -73,27 +59,45 @@ int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id) return 0; } -int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id) +int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id, + const struct phylink_link_state *state) { unsigned int val; - int mode; if (!ss->regmap[id]) return -EINVAL; regmap_read(ss->regmap[id], ss->ana_rgc3, &val); - val &= ~GENMASK(3, 2); - mode = ss->flags[id] & MTK_SGMII_PHYSPEED_MASK; - val |= (mode == MTK_SGMII_PHYSPEED_1000) ? 0 : BIT(2); + val &= ~RG_PHY_SPEED_MASK; + if (state->interface == PHY_INTERFACE_MODE_2500BASEX) + val |= RG_PHY_SPEED_3_125G; regmap_write(ss->regmap[id], ss->ana_rgc3, val); /* Disable SGMII AN */ regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val); - val &= ~BIT(12); + val &= ~SGMII_AN_ENABLE; regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val); /* SGMII force mode setting */ - val = 0x31120019; + regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val); + val &= ~SGMII_IF_MODE_MASK; + + switch (state->speed) { + case SPEED_10: + val |= SGMII_SPEED_10; + break; + case SPEED_100: + val |= SGMII_SPEED_100; + break; + case SPEED_2500: + case SPEED_1000: + val |= SGMII_SPEED_1000; + break; + }; + + if (state->duplex == DUPLEX_FULL) + val |= SGMII_DUPLEX_FULL; + regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val); /* Release PHYA power down state */ @@ -103,3 +107,20 @@ int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id) return 0; } + +void mtk_sgmii_restart_an(struct mtk_eth *eth, int mac_id) +{ + struct mtk_sgmii *ss = eth->sgmii; + unsigned int val, sid; + + /* Decide how GMAC and SGMIISYS be mapped */ + sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ? + 0 : mac_id; + + if (!ss->regmap[sid]) + return; + + regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val); + val |= SGMII_AN_RESTART; + regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val); +} -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1418C3A5A1 for ; Sun, 25 Aug 2019 17:44:46 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B2CC6206DD for ; Sun, 25 Aug 2019 17:44:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="BV/70pat"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=vdorst.com header.i=@vdorst.com header.b="atwT2QMT" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B2CC6206DD Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=vdorst.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=8JY7lxu/3LU7m3c09U80VQHhiiO3eFW/CCYm3JVv0zw=; b=BV/70patwwcM6d AaIpeV9f1jx7si6JUSo/eE0i9GEGLwtOVy4LrC7t3Fsmv16KYc0EChiMSnNZt0TPi9Sp9GsWoY4ID rmaw+2or+8qth1xz/00fVDobZJxECc1b7AXwrruQmRS4SVu3e+prQSRvpiki5nDmYen/KLfmq7dxQ C0cmrQSMz42aRgjZweCcLv/oyCAoaZ7WAYbr9JecuS5rfK0Il+rV19Zd9dG6NSMaynW9PU/Lismn5 i424m6D7FuQ7PmCsUYzpck6zOUDkZ5DBgCGblIdDtDyyQM2runwnMHjgym0ZfG/8uZY8wZDx67JrN 5gD/dV1OogUvaFN/W+Lw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1i1wZC-0007MK-Uf; Sun, 25 Aug 2019 17:44:39 +0000 Received: from mx.0dd.nl ([5.2.79.48]) by bombadil.infradead.org with esmtp (Exim 4.92 #3 (Red Hat Linux)) id 1i1wYY-0006iG-3X; Sun, 25 Aug 2019 17:44:02 +0000 Received: from mail.vdorst.com (mail.vdorst.com [IPv6:fd01::250]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.0dd.nl (Postfix) with ESMTPS id 4224B5FD0D; Sun, 25 Aug 2019 19:43:55 +0200 (CEST) Authentication-Results: mx.0dd.nl; dkim=pass (2048-bit key) header.d=vdorst.com header.i=@vdorst.com header.b="atwT2QMT"; dkim-atps=neutral Received: from pc-rene.vdorst.com (pc-rene.vdorst.com [192.168.2.125]) by mail.vdorst.com (Postfix) with ESMTPA id 057331D8E166; Sun, 25 Aug 2019 19:43:55 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.vdorst.com 057331D8E166 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vdorst.com; s=default; t=1566755035; bh=7ebJM33QQ0k5xG40NPef/hKLC+qMN+E9QE4LSvqBjWc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=atwT2QMTxyYUN19XGlgbDkFLFBiYj8ZedhZXSHqJPZb2ihi0R+TXrtrTRXbJUTg8q H12gJrZ1AU9hm3z58r2/5GJbqY3/WJRwzJ1kFRqELQnHHAVTHYVPAEShX8cfqfdWS5 LiCyZdKyo+Sl2CBrStr/9iAxoGu8vg61eEtXA7QQVl5QkIaPejzpyVhknJW1k4wFD6 ByQV33qkdmrLgUTEPGemtDxr2hsrqWwzlsg5DGf76+zIEAtfMPVLTSfMmIa60Az5l1 jnJ3bIAL8GaZxvR0fksdM7K9O7IZMuRZdXeDVHPtEarPcmwmoDYZnbFyDV+09M+DcG 0v4OB4yDpdWyg== From: =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= To: John Crispin , Sean Wang , Nelson Chang , "David S . Miller" , Matthias Brugger Subject: [PATCH net-next v4 2/3] net: ethernet: mediatek: Re-add support SGMII Date: Sun, 25 Aug 2019 19:43:40 +0200 Message-Id: <20190825174341.20750-3-opensource@vdorst.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190825174341.20750-1-opensource@vdorst.com> References: <20190825174341.20750-1-opensource@vdorst.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190825_104358_436797_0A935F51 X-CRM114-Status: GOOD ( 20.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Wunderlich , netdev@vger.kernel.org, linux-mips@vger.kernel.org, Russell King , =?UTF-8?q?Ren=C3=A9=20van=20Dorst?= , linux-mediatek@lists.infradead.org, Stefan Roese , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org KiBSZS1hZGQgU0dNSUkgc3VwcG9ydCBidXQgbm93IHdpdGggUEhZTElOSyBBUEkgc3VwcG9ydAog IFNvIHRoZSBTR01JSSBjaGFuZ2VzIGFyZSBtb3JlIGNsZWFyCiogTW92ZSBTR01JSSBibG9jayBz ZXR1cCBmcm9tIG10a19nbWFjX3NnbWlpX3BhdGhfc2V0dXAoKSB0bwogIG10a19tYWNfY29uZmln KCkKKiBNZXJnZSBtdGtfc2V0dXBfaHdfcGF0aCgpIGludG8gbXRrX21hY19jb25maWcoKQoqIFJl bW92ZSBtZWRpYXRlayxwaHlzcGVlZCBwcm9wZXJ0eSwgZml4ZWQtbGluayBzdXBwb3J0cyBub3cg YW55IHNwZWVkIHNvCiAgc3BlZWQgPSA8MjUwMD47IGlzIG5vdyB2YWxpZCB3aXRoIFBIWUxJTksK KiBEZW1hZ2ljIFNHTUlJIHJlZ2lzdGVyIHZhbHVlcwoqIFVzZSBwaHlsaW5rIHN0YXRlIHRvIHNl dHVwIGZpeGVkLWxpbmsgbW9kZQoKU2lnbmVkLW9mZi1ieTogUmVuw6kgdmFuIERvcnN0IDxvcGVu c291cmNlQHZkb3JzdC5jb20+Ci0tCnYzLT52NDoKKiBSZWZhY3RvciB2YWxpZGF0ZSgpIHRvIGlu Y29ycG9yYXRlIHRoZSBmb2xsb3dpbmcgaXRlbXMuCiogQWxzbyByZXBvcnQgMTAwMGJhc2VYX0Z1 bGwgZm9yIFNHTUlJIGFuZCBHTUlJIG1vZGVzLgogIFN1Z2dlc3RlZCBieSBSdXNzZWxsIEtpbmcK KiBSZXBvcnQgYm90aCAxMDAwQmFzZVggYW5kIDI1MDBCYXNlWCBtb2RlcyBpbiBib3RoIEJhc2VY IG1vZGUuCiAgQXMgUnVzc3NlbGwgS2luZyBleHBsYWlucyBoZXJlOgogIGh0dHBzOi8vbG9yZS5r ZXJuZWwub3JnL25ldGRldi8yMDE5MDgyNDA5MTEwNi5HQzEzMjk0QHNoZWxsLmFybWxpbnV4Lm9y Zy51ay8KdjItPnYzOgoqIFJlZG8gdmFsaWRhdGUoKSwgaXQgd2FzIHRvdGFsbHkgd3JvbmcuIE5v dGljZWQgYnkgUnVzc2VsbCBLaW5nLgp2MS0+djI6CiogU0dNSUkgcG9ydCBvbmx5IHN1cHBvcnQg U0dNSUkgYXQgMUdiaXQsIDEwMDBCQVNFLVggYW5kIDI1MDBCQVNFLVguCiAgQWxzbyBTR01JSSBt b2RlIG9ubHkgZG9lcyBhdXRvLW5lZ290aWF0aW9uLgoqIENoYW5nZSB2YWxpZGF0ZSgpIHRvIHN1 cHBvcnQgbXQ3Nng4IGNoYW5nZXMuCi0tLQogZHJpdmVycy9uZXQvZXRoZXJuZXQvbWVkaWF0ZWsv bXRrX2V0aF9wYXRoLmMgfCAgNzUgKy0tLS0tLS0tCiBkcml2ZXJzL25ldC9ldGhlcm5ldC9tZWRp YXRlay9tdGtfZXRoX3NvYy5jICB8IDE1MSArKysrKysrKysrKysrKysrLS0tCiBkcml2ZXJzL25l dC9ldGhlcm5ldC9tZWRpYXRlay9tdGtfZXRoX3NvYy5oICB8ICAzNyArKysrLQogZHJpdmVycy9u ZXQvZXRoZXJuZXQvbWVkaWF0ZWsvbXRrX3NnbWlpLmMgICAgfCAgNjUgKysrKystLS0KIDQgZmls ZXMgY2hhbmdlZCwgMjEzIGluc2VydGlvbnMoKyksIDExNSBkZWxldGlvbnMoLSkKCmRpZmYgLS1n aXQgYS9kcml2ZXJzL25ldC9ldGhlcm5ldC9tZWRpYXRlay9tdGtfZXRoX3BhdGguYyBiL2RyaXZl cnMvbmV0L2V0aGVybmV0L21lZGlhdGVrL210a19ldGhfcGF0aC5jCmluZGV4IDI4OTYwZTRjNGU0 My4uZWYxMWNmM2QxY2NjIDEwMDY0NAotLS0gYS9kcml2ZXJzL25ldC9ldGhlcm5ldC9tZWRpYXRl ay9tdGtfZXRoX3BhdGguYworKysgYi9kcml2ZXJzL25ldC9ldGhlcm5ldC9tZWRpYXRlay9tdGtf ZXRoX3BhdGguYwpAQCAtMjM5LDEwICsyMzksOSBAQCBzdGF0aWMgaW50IG10a19ldGhfbXV4X3Nl dHVwKHN0cnVjdCBtdGtfZXRoICpldGgsIGludCBwYXRoKQogCXJldHVybiBlcnI7CiB9CiAKLXN0 YXRpYyBpbnQgbXRrX2dtYWNfc2dtaWlfcGF0aF9zZXR1cChzdHJ1Y3QgbXRrX2V0aCAqZXRoLCBp bnQgbWFjX2lkKQoraW50IG10a19nbWFjX3NnbWlpX3BhdGhfc2V0dXAoc3RydWN0IG10a19ldGgg KmV0aCwgaW50IG1hY19pZCkKIHsKLQl1bnNpZ25lZCBpbnQgdmFsID0gMDsKLQlpbnQgc2lkLCBl cnIsIHBhdGg7CisJaW50IGVyciwgcGF0aDsKIAogCXBhdGggPSAobWFjX2lkID09IDApID8gIE1U S19FVEhfUEFUSF9HTUFDMV9TR01JSSA6CiAJCQkJTVRLX0VUSF9QQVRIX0dNQUMyX1NHTUlJOwpA QCAtMjUyLDMzICsyNTEsMTAgQEAgc3RhdGljIGludCBtdGtfZ21hY19zZ21paV9wYXRoX3NldHVw KHN0cnVjdCBtdGtfZXRoICpldGgsIGludCBtYWNfaWQpCiAJaWYgKGVycikKIAkJcmV0dXJuIGVy cjsKIAotCS8qIFRoZSBwYXRoIEdNQUMgdG8gU0dNSUkgd2lsbCBiZSBlbmFibGVkIG9uY2UgdGhl IFNHTUlJU1lTIGlzIGJlaW5nCi0JICogc2V0dXAgZG9uZS4KLQkgKi8KLQlyZWdtYXBfcmVhZChl dGgtPmV0aHN5cywgRVRIU1lTX1NZU0NGRzAsICZ2YWwpOwotCi0JcmVnbWFwX3VwZGF0ZV9iaXRz KGV0aC0+ZXRoc3lzLCBFVEhTWVNfU1lTQ0ZHMCwKLQkJCSAgIFNZU0NGRzBfU0dNSUlfTUFTSywg fih1MzIpU1lTQ0ZHMF9TR01JSV9NQVNLKTsKLQotCS8qIERlY2lkZSBob3cgR01BQyBhbmQgU0dN SUlTWVMgYmUgbWFwcGVkICovCi0Jc2lkID0gKE1US19IQVNfQ0FQUyhldGgtPnNvYy0+Y2Fwcywg TVRLX1NIQVJFRF9TR01JSSkpID8gMCA6IG1hY19pZDsKLQotCS8qIFNldHVwIFNHTUlJU1lTIHdp dGggdGhlIGRldGVybWluZWQgcHJvcGVydHkgKi8KLQlpZiAoTVRLX0hBU19GTEFHUyhldGgtPnNn bWlpLT5mbGFnc1tzaWRdLCBNVEtfU0dNSUlfUEhZU1BFRURfQU4pKQotCQllcnIgPSBtdGtfc2dt aWlfc2V0dXBfbW9kZV9hbihldGgtPnNnbWlpLCBzaWQpOwotCWVsc2UKLQkJZXJyID0gbXRrX3Nn bWlpX3NldHVwX21vZGVfZm9yY2UoZXRoLT5zZ21paSwgc2lkKTsKLQotCWlmIChlcnIpCi0JCXJl dHVybiBlcnI7Ci0KLQlyZWdtYXBfdXBkYXRlX2JpdHMoZXRoLT5ldGhzeXMsIEVUSFNZU19TWVND RkcwLAotCQkJICAgU1lTQ0ZHMF9TR01JSV9NQVNLLCB2YWwpOwotCiAJcmV0dXJuIDA7CiB9CiAK LXN0YXRpYyBpbnQgbXRrX2dtYWNfZ2VwaHlfcGF0aF9zZXR1cChzdHJ1Y3QgbXRrX2V0aCAqZXRo LCBpbnQgbWFjX2lkKQoraW50IG10a19nbWFjX2dlcGh5X3BhdGhfc2V0dXAoc3RydWN0IG10a19l dGggKmV0aCwgaW50IG1hY19pZCkKIHsKIAlpbnQgZXJyLCBwYXRoID0gMDsKIApAQCAtMjk2LDcg KzI3Miw3IEBAIHN0YXRpYyBpbnQgbXRrX2dtYWNfZ2VwaHlfcGF0aF9zZXR1cChzdHJ1Y3QgbXRr X2V0aCAqZXRoLCBpbnQgbWFjX2lkKQogCXJldHVybiAwOwogfQogCi1zdGF0aWMgaW50IG10a19n bWFjX3JnbWlpX3BhdGhfc2V0dXAoc3RydWN0IG10a19ldGggKmV0aCwgaW50IG1hY19pZCkKK2lu dCBtdGtfZ21hY19yZ21paV9wYXRoX3NldHVwKHN0cnVjdCBtdGtfZXRoICpldGgsIGludCBtYWNf aWQpCiB7CiAJaW50IGVyciwgcGF0aDsKIApAQCAtMzExLDQ2ICsyODcsMyBAQCBzdGF0aWMgaW50 IG10a19nbWFjX3JnbWlpX3BhdGhfc2V0dXAoc3RydWN0IG10a19ldGggKmV0aCwgaW50IG1hY19p ZCkKIAlyZXR1cm4gMDsKIH0KIAotaW50IG10a19zZXR1cF9od19wYXRoKHN0cnVjdCBtdGtfZXRo ICpldGgsIGludCBtYWNfaWQsIGludCBwaHltb2RlKQotewotCWludCBlcnI7Ci0KLQkvKiBObyBt dXgnaW5nIGZvciBNVDc2MjgvODggKi8KLQlpZiAoTVRLX0hBU19DQVBTKGV0aC0+c29jLT5jYXBz LCBNVEtfU09DX01UNzYyOCkpCi0JCXJldHVybiAwOwotCi0Jc3dpdGNoIChwaHltb2RlKSB7Ci0J Y2FzZSBQSFlfSU5URVJGQUNFX01PREVfVFJHTUlJOgotCWNhc2UgUEhZX0lOVEVSRkFDRV9NT0RF X1JHTUlJX1RYSUQ6Ci0JY2FzZSBQSFlfSU5URVJGQUNFX01PREVfUkdNSUlfUlhJRDoKLQljYXNl IFBIWV9JTlRFUkZBQ0VfTU9ERV9SR01JSV9JRDoKLQljYXNlIFBIWV9JTlRFUkZBQ0VfTU9ERV9S R01JSToKLQljYXNlIFBIWV9JTlRFUkZBQ0VfTU9ERV9NSUk6Ci0JY2FzZSBQSFlfSU5URVJGQUNF X01PREVfUkVWTUlJOgotCWNhc2UgUEhZX0lOVEVSRkFDRV9NT0RFX1JNSUk6Ci0JCWlmIChNVEtf SEFTX0NBUFMoZXRoLT5zb2MtPmNhcHMsIE1US19SR01JSSkpIHsKLQkJCWVyciA9IG10a19nbWFj X3JnbWlpX3BhdGhfc2V0dXAoZXRoLCBtYWNfaWQpOwotCQkJaWYgKGVycikKLQkJCQlyZXR1cm4g ZXJyOwotCQl9Ci0JCWJyZWFrOwotCWNhc2UgUEhZX0lOVEVSRkFDRV9NT0RFX1NHTUlJOgotCQlp ZiAoTVRLX0hBU19DQVBTKGV0aC0+c29jLT5jYXBzLCBNVEtfU0dNSUkpKSB7Ci0JCQllcnIgPSBt dGtfZ21hY19zZ21paV9wYXRoX3NldHVwKGV0aCwgbWFjX2lkKTsKLQkJCWlmIChlcnIpCi0JCQkJ cmV0dXJuIGVycjsKLQkJfQotCQlicmVhazsKLQljYXNlIFBIWV9JTlRFUkZBQ0VfTU9ERV9HTUlJ OgotCQlpZiAoTVRLX0hBU19DQVBTKGV0aC0+c29jLT5jYXBzLCBNVEtfR0VQSFkpKSB7Ci0JCQll cnIgPSBtdGtfZ21hY19nZXBoeV9wYXRoX3NldHVwKGV0aCwgbWFjX2lkKTsKLQkJCWlmIChlcnIp Ci0JCQkJcmV0dXJuIGVycjsKLQkJfQotCQlicmVhazsKLQlkZWZhdWx0OgotCQlicmVhazsKLQl9 Ci0KLQlyZXR1cm4gMDsKLX0KZGlmZiAtLWdpdCBhL2RyaXZlcnMvbmV0L2V0aGVybmV0L21lZGlh dGVrL210a19ldGhfc29jLmMgYi9kcml2ZXJzL25ldC9ldGhlcm5ldC9tZWRpYXRlay9tdGtfZXRo X3NvYy5jCmluZGV4IDdkMjU2NmRkNGNlMC4uYjQxODg0ZTEyNDM0IDEwMDY0NAotLS0gYS9kcml2 ZXJzL25ldC9ldGhlcm5ldC9tZWRpYXRlay9tdGtfZXRoX3NvYy5jCisrKyBiL2RyaXZlcnMvbmV0 L2V0aGVybmV0L21lZGlhdGVrL210a19ldGhfc29jLmMKQEAgLTE5Myw4ICsxOTMsOCBAQCBzdGF0 aWMgdm9pZCBtdGtfbWFjX2NvbmZpZyhzdHJ1Y3QgcGh5bGlua19jb25maWcgKmNvbmZpZywgdW5z aWduZWQgaW50IG1vZGUsCiAJc3RydWN0IG10a19tYWMgKm1hYyA9IGNvbnRhaW5lcl9vZihjb25m aWcsIHN0cnVjdCBtdGtfbWFjLAogCQkJCQkgICBwaHlsaW5rX2NvbmZpZyk7CiAJc3RydWN0IG10 a19ldGggKmV0aCA9IG1hYy0+aHc7Ci0JdTMyIG1jcl9jdXIsIG1jcl9uZXc7Ci0JaW50IHZhbCwg Z2VfbW9kZSA9IDA7CisJdTMyIG1jcl9jdXIsIG1jcl9uZXcsIHNpZDsKKwlpbnQgdmFsLCBnZV9t b2RlLCBlcnI7CiAKIAkvKiBNVDc2eDggaGFzIG5vIGhhcmR3YXJlIHNldHRpbmdzIGJldHdlZW4g Zm9yIHRoZSBNQUMgKi8KIAlpZiAoIU1US19IQVNfQ0FQUyhldGgtPnNvYy0+Y2FwcywgTVRLX1NP Q19NVDc2MjgpICYmCkBAIC0yMDgsMjkgKzIwOCw0MiBAQCBzdGF0aWMgdm9pZCBtdGtfbWFjX2Nv bmZpZyhzdHJ1Y3QgcGh5bGlua19jb25maWcgKmNvbmZpZywgdW5zaWduZWQgaW50IG1vZGUsCiAJ CQkJCSAgTVRLX0dNQUMxX1RSR01JSSkpCiAJCQkJZ290byBlcnJfcGh5OwogCQkJLyogZmFsbCB0 aHJvdWdoICovCi0JCWNhc2UgUEhZX0lOVEVSRkFDRV9NT0RFX0dNSUk6CiAJCWNhc2UgUEhZX0lO VEVSRkFDRV9NT0RFX1JHTUlJX1RYSUQ6CiAJCWNhc2UgUEhZX0lOVEVSRkFDRV9NT0RFX1JHTUlJ X1JYSUQ6CiAJCWNhc2UgUEhZX0lOVEVSRkFDRV9NT0RFX1JHTUlJX0lEOgogCQljYXNlIFBIWV9J TlRFUkZBQ0VfTU9ERV9SR01JSToKLQkJCWJyZWFrOwogCQljYXNlIFBIWV9JTlRFUkZBQ0VfTU9E RV9NSUk6Ci0JCQlnZV9tb2RlID0gMTsKLQkJCWJyZWFrOwogCQljYXNlIFBIWV9JTlRFUkZBQ0Vf TU9ERV9SRVZNSUk6Ci0JCQlnZV9tb2RlID0gMjsKLQkJCWJyZWFrOwogCQljYXNlIFBIWV9JTlRF UkZBQ0VfTU9ERV9STUlJOgotCQkJaWYgKG1hYy0+aWQpCi0JCQkJZ290byBlcnJfcGh5OwotCQkJ Z2VfbW9kZSA9IDM7CisJCQlpZiAoTVRLX0hBU19DQVBTKGV0aC0+c29jLT5jYXBzLCBNVEtfUkdN SUkpKSB7CisJCQkJZXJyID0gbXRrX2dtYWNfcmdtaWlfcGF0aF9zZXR1cChldGgsIG1hYy0+aWQp OworCQkJCWlmIChlcnIpCisJCQkJCWdvdG8gaW5pdF9lcnI7CisJCQl9CisJCQlicmVhazsKKwkJ Y2FzZSBQSFlfSU5URVJGQUNFX01PREVfMTAwMEJBU0VYOgorCQljYXNlIFBIWV9JTlRFUkZBQ0Vf TU9ERV8yNTAwQkFTRVg6CisJCWNhc2UgUEhZX0lOVEVSRkFDRV9NT0RFX1NHTUlJOgorCQkJaWYg KE1US19IQVNfQ0FQUyhldGgtPnNvYy0+Y2FwcywgTVRLX1NHTUlJKSkgeworCQkJCWVyciA9IG10 a19nbWFjX3NnbWlpX3BhdGhfc2V0dXAoZXRoLCBtYWMtPmlkKTsKKwkJCQlpZiAoZXJyKQorCQkJ CQlnb3RvIGluaXRfZXJyOworCQkJfQorCQkJYnJlYWs7CisJCWNhc2UgUEhZX0lOVEVSRkFDRV9N T0RFX0dNSUk6CisJCQlpZiAoTVRLX0hBU19DQVBTKGV0aC0+c29jLT5jYXBzLCBNVEtfR0VQSFkp KSB7CisJCQkJZXJyID0gbXRrX2dtYWNfZ2VwaHlfcGF0aF9zZXR1cChldGgsIG1hYy0+aWQpOwor CQkJCWlmIChlcnIpCisJCQkJCWdvdG8gaW5pdF9lcnI7CisJCQl9CiAJCQlicmVhazsKIAkJZGVm YXVsdDoKIAkJCWdvdG8gZXJyX3BoeTsKIAkJfQogCiAJCS8qIFNldHVwIGNsb2NrIGZvciAxc3Qg Z21hYyAqLwotCQlpZiAoIW1hYy0+aWQgJiYKKwkJaWYgKCFtYWMtPmlkICYmIHN0YXRlLT5pbnRl cmZhY2UgIT0gUEhZX0lOVEVSRkFDRV9NT0RFX1NHTUlJICYmCisJCSAgICAhcGh5X2ludGVyZmFj ZV9tb2RlX2lzXzgwMjN6KHN0YXRlLT5pbnRlcmZhY2UpICYmCiAJCSAgICBNVEtfSEFTX0NBUFMo bWFjLT5ody0+c29jLT5jYXBzLCBNVEtfR01BQzFfVFJHTUlJKSkgewogCQkJaWYgKE1US19IQVNf Q0FQUyhtYWMtPmh3LT5zb2MtPmNhcHMsCiAJCQkJCSBNVEtfVFJHTUlJX01UNzYyMV9DTEspKSB7 CkBAIC0yNDUsNiArMjU4LDIzIEBAIHN0YXRpYyB2b2lkIG10a19tYWNfY29uZmlnKHN0cnVjdCBw aHlsaW5rX2NvbmZpZyAqY29uZmlnLCB1bnNpZ25lZCBpbnQgbW9kZSwKIAkJCX0KIAkJfQogCisJ CWdlX21vZGUgPSAwOworCQlzd2l0Y2ggKHN0YXRlLT5pbnRlcmZhY2UpIHsKKwkJY2FzZSBQSFlf SU5URVJGQUNFX01PREVfTUlJOgorCQkJZ2VfbW9kZSA9IDE7CisJCQlicmVhazsKKwkJY2FzZSBQ SFlfSU5URVJGQUNFX01PREVfUkVWTUlJOgorCQkJZ2VfbW9kZSA9IDI7CisJCQlicmVhazsKKwkJ Y2FzZSBQSFlfSU5URVJGQUNFX01PREVfUk1JSToKKwkJCWlmIChtYWMtPmlkKQorCQkJCWdvdG8g ZXJyX3BoeTsKKwkJCWdlX21vZGUgPSAzOworCQkJYnJlYWs7CisJCWRlZmF1bHQ6CisJCQlicmVh azsKKwkJfQorCiAJCS8qIHB1dCB0aGUgZ21hYyBpbnRvIHRoZSByaWdodCBtb2RlICovCiAJCXJl Z21hcF9yZWFkKGV0aC0+ZXRoc3lzLCBFVEhTWVNfU1lTQ0ZHMCwgJnZhbCk7CiAJCXZhbCAmPSB+ U1lTQ0ZHMF9HRV9NT0RFKFNZU0NGRzBfR0VfTUFTSywgbWFjLT5pZCk7CkBAIC0yNTQsNiArMjg0 LDQwIEBAIHN0YXRpYyB2b2lkIG10a19tYWNfY29uZmlnKHN0cnVjdCBwaHlsaW5rX2NvbmZpZyAq Y29uZmlnLCB1bnNpZ25lZCBpbnQgbW9kZSwKIAkJbWFjLT5pbnRlcmZhY2UgPSBzdGF0ZS0+aW50 ZXJmYWNlOwogCX0KIAorCS8qIFNHTUlJICovCisJaWYgKHN0YXRlLT5pbnRlcmZhY2UgPT0gUEhZ X0lOVEVSRkFDRV9NT0RFX1NHTUlJIHx8CisJICAgIHBoeV9pbnRlcmZhY2VfbW9kZV9pc184MDIz eihzdGF0ZS0+aW50ZXJmYWNlKSkgeworCQkvKiBUaGUgcGF0aCBHTUFDIHRvIFNHTUlJIHdpbGwg YmUgZW5hYmxlZCBvbmNlIHRoZSBTR01JSVNZUyBpcworCQkgKiBiZWluZyBzZXR1cCBkb25lLgor CQkgKi8KKwkJcmVnbWFwX3JlYWQoZXRoLT5ldGhzeXMsIEVUSFNZU19TWVNDRkcwLCAmdmFsKTsK KworCQlyZWdtYXBfdXBkYXRlX2JpdHMoZXRoLT5ldGhzeXMsIEVUSFNZU19TWVNDRkcwLAorCQkJ CSAgIFNZU0NGRzBfU0dNSUlfTUFTSywKKwkJCQkgICB+KHUzMilTWVNDRkcwX1NHTUlJX01BU0sp OworCisJCS8qIERlY2lkZSBob3cgR01BQyBhbmQgU0dNSUlTWVMgYmUgbWFwcGVkICovCisJCXNp ZCA9IChNVEtfSEFTX0NBUFMoZXRoLT5zb2MtPmNhcHMsIE1US19TSEFSRURfU0dNSUkpKSA/CisJ CSAgICAgICAwIDogbWFjLT5pZDsKKworCQkvKiBTZXR1cCBTR01JSVNZUyB3aXRoIHRoZSBkZXRl cm1pbmVkIHByb3BlcnR5ICovCisJCWlmIChzdGF0ZS0+aW50ZXJmYWNlICE9IFBIWV9JTlRFUkZB Q0VfTU9ERV9TR01JSSkKKwkJCWVyciA9IG10a19zZ21paV9zZXR1cF9tb2RlX2ZvcmNlKGV0aC0+ c2dtaWksIHNpZCwKKwkJCQkJCQkgc3RhdGUpOworCQllbHNlIGlmIChwaHlsaW5rX2F1dG9uZWdf aW5iYW5kKG1vZGUpKQorCQkJZXJyID0gbXRrX3NnbWlpX3NldHVwX21vZGVfYW4oZXRoLT5zZ21p aSwgc2lkKTsKKworCQlpZiAoZXJyKQorCQkJZ290byBpbml0X2VycjsKKworCQlyZWdtYXBfdXBk YXRlX2JpdHMoZXRoLT5ldGhzeXMsIEVUSFNZU19TWVNDRkcwLAorCQkJCSAgIFNZU0NGRzBfU0dN SUlfTUFTSywgdmFsKTsKKwl9IGVsc2UgaWYgKHBoeWxpbmtfYXV0b25lZ19pbmJhbmQobW9kZSkp IHsKKwkJZGV2X2VycihldGgtPmRldiwKKwkJCSJJbi1iYW5kIG1vZGUgbm90IHN1cHBvcnRlZCBp biBub24gU0dNSUkgbW9kZSFcbiIpOworCQlyZXR1cm47CisJfQorCiAJLyogU2V0dXAgZ21hYyAq LwogCW1jcl9jdXIgPSBtdGtfcjMyKG1hYy0+aHcsIE1US19NQUNfTUNSKG1hYy0+aWQpKTsKIAlt Y3JfbmV3ID0gbWNyX2N1cjsKQEAgLTI2NCw2ICszMjgsNyBAQCBzdGF0aWMgdm9pZCBtdGtfbWFj X2NvbmZpZyhzdHJ1Y3QgcGh5bGlua19jb25maWcgKmNvbmZpZywgdW5zaWduZWQgaW50IG1vZGUs CiAJCSAgIE1BQ19NQ1JfQkFDS09GRl9FTiB8IE1BQ19NQ1JfQkFDS1BSX0VOIHwgTUFDX01DUl9G T1JDRV9MSU5LOwogCiAJc3dpdGNoIChzdGF0ZS0+c3BlZWQpIHsKKwljYXNlIFNQRUVEXzI1MDA6 CiAJY2FzZSBTUEVFRF8xMDAwOgogCQltY3JfbmV3IHw9IE1BQ19NQ1JfU1BFRURfMTAwMDsKIAkJ YnJlYWs7CkBAIC0yODgsNiArMzUzLDExIEBAIHN0YXRpYyB2b2lkIG10a19tYWNfY29uZmlnKHN0 cnVjdCBwaHlsaW5rX2NvbmZpZyAqY29uZmlnLCB1bnNpZ25lZCBpbnQgbW9kZSwKIGVycl9waHk6 CiAJZGV2X2VycihldGgtPmRldiwgIiVzOiBHTUFDJWQgbW9kZSAlcyBub3Qgc3VwcG9ydGVkIVxu IiwgX19mdW5jX18sCiAJCW1hYy0+aWQsIHBoeV9tb2RlcyhzdGF0ZS0+aW50ZXJmYWNlKSk7CisJ cmV0dXJuOworCitpbml0X2VycjoKKwlkZXZfZXJyKGV0aC0+ZGV2LCAiJXM6IEdNQUMlZCBtb2Rl ICVzIGVycjogJWQhXG4iLCBfX2Z1bmNfXywKKwkJbWFjLT5pZCwgcGh5X21vZGVzKHN0YXRlLT5p bnRlcmZhY2UpLCBlcnIpOwogfQogCiBzdGF0aWMgaW50IG10a19tYWNfbGlua19zdGF0ZShzdHJ1 Y3QgcGh5bGlua19jb25maWcgKmNvbmZpZywKQEAgLTMyNiw3ICszOTYsMTAgQEAgc3RhdGljIGlu dCBtdGtfbWFjX2xpbmtfc3RhdGUoc3RydWN0IHBoeWxpbmtfY29uZmlnICpjb25maWcsCiAKIHN0 YXRpYyB2b2lkIG10a19tYWNfYW5fcmVzdGFydChzdHJ1Y3QgcGh5bGlua19jb25maWcgKmNvbmZp ZykKIHsKLQkvKiBEbyBub3RoaW5nICovCisJc3RydWN0IG10a19tYWMgKm1hYyA9IGNvbnRhaW5l cl9vZihjb25maWcsIHN0cnVjdCBtdGtfbWFjLAorCQkJCQkgICBwaHlsaW5rX2NvbmZpZyk7CisK KwltdGtfc2dtaWlfcmVzdGFydF9hbihtYWMtPmh3LCBtYWMtPmlkKTsKIH0KIAogc3RhdGljIHZv aWQgbXRrX21hY19saW5rX2Rvd24oc3RydWN0IHBoeWxpbmtfY29uZmlnICpjb25maWcsIHVuc2ln bmVkIGludCBtb2RlLApAQCAtMzY2LDcgKzQzOSwxMCBAQCBzdGF0aWMgdm9pZCBtdGtfdmFsaWRh dGUoc3RydWN0IHBoeWxpbmtfY29uZmlnICpjb25maWcsCiAJICAgICEoTVRLX0hBU19DQVBTKG1h Yy0+aHctPnNvYy0+Y2FwcywgTVRLX1JHTUlJKSAmJgogCSAgICAgIHBoeV9pbnRlcmZhY2VfbW9k ZV9pc19yZ21paShzdGF0ZS0+aW50ZXJmYWNlKSkgJiYKIAkgICAgIShNVEtfSEFTX0NBUFMobWFj LT5ody0+c29jLT5jYXBzLCBNVEtfVFJHTUlJKSAmJgotCSAgICAgICFtYWMtPmlkICYmIHN0YXRl LT5pbnRlcmZhY2UgPT0gUEhZX0lOVEVSRkFDRV9NT0RFX1RSR01JSSkpIHsKKwkgICAgICAhbWFj LT5pZCAmJiBzdGF0ZS0+aW50ZXJmYWNlID09IFBIWV9JTlRFUkZBQ0VfTU9ERV9UUkdNSUkpICYm CisJICAgICEoTVRLX0hBU19DQVBTKG1hYy0+aHctPnNvYy0+Y2FwcywgTVRLX1NHTUlJKSAmJgor CSAgICAgIChzdGF0ZS0+aW50ZXJmYWNlID09IFBIWV9JTlRFUkZBQ0VfTU9ERV9TR01JSSB8fAor CSAgICAgICBwaHlfaW50ZXJmYWNlX21vZGVfaXNfODAyM3ooc3RhdGUtPmludGVyZmFjZSkpKSkg ewogCQlsaW5rbW9kZV96ZXJvKHN1cHBvcnRlZCk7CiAJCXJldHVybjsKIAl9CkBAIC0zNzQsMTkg KzQ1MCw1MyBAQCBzdGF0aWMgdm9pZCBtdGtfdmFsaWRhdGUoc3RydWN0IHBoeWxpbmtfY29uZmln ICpjb25maWcsCiAJcGh5bGlua19zZXRfcG9ydF9tb2RlcyhtYXNrKTsKIAlwaHlsaW5rX3NldCht YXNrLCBBdXRvbmVnKTsKIAotCWlmIChzdGF0ZS0+aW50ZXJmYWNlID09IFBIWV9JTlRFUkZBQ0Vf TU9ERV9UUkdNSUkpIHsKKwlzd2l0Y2ggKHN0YXRlLT5pbnRlcmZhY2UpIHsKKwljYXNlIFBIWV9J TlRFUkZBQ0VfTU9ERV9UUkdNSUk6CiAJCXBoeWxpbmtfc2V0KG1hc2ssIDEwMDBiYXNlVF9GdWxs KTsKLQl9IGVsc2UgeworCQlicmVhazsKKwljYXNlIFBIWV9JTlRFUkZBQ0VfTU9ERV8xMDAwQkFT RVg6CisJY2FzZSBQSFlfSU5URVJGQUNFX01PREVfMjUwMEJBU0VYOgorCQlwaHlsaW5rX3NldCht YXNrLCAxMDAwYmFzZVhfRnVsbCk7CisJCXBoeWxpbmtfc2V0KG1hc2ssIDI1MDBiYXNlWF9GdWxs KTsKKwkJYnJlYWs7CisJY2FzZSBQSFlfSU5URVJGQUNFX01PREVfR01JSToKKwljYXNlIFBIWV9J TlRFUkZBQ0VfTU9ERV9SR01JSToKKwljYXNlIFBIWV9JTlRFUkZBQ0VfTU9ERV9SR01JSV9JRDoK KwljYXNlIFBIWV9JTlRFUkZBQ0VfTU9ERV9SR01JSV9SWElEOgorCWNhc2UgUEhZX0lOVEVSRkFD RV9NT0RFX1JHTUlJX1RYSUQ6CisJCXBoeWxpbmtfc2V0KG1hc2ssIDEwMDBiYXNlVF9IYWxmKTsK KwkJLyogZmFsbCB0aHJvdWdoICovCisJY2FzZSBQSFlfSU5URVJGQUNFX01PREVfU0dNSUk6CisJ CXBoeWxpbmtfc2V0KG1hc2ssIDEwMDBiYXNlVF9GdWxsKTsKKwkJcGh5bGlua19zZXQobWFzaywg MTAwMGJhc2VYX0Z1bGwpOworCQkvKiBmYWxsIHRocm91Z2ggKi8KKwljYXNlIFBIWV9JTlRFUkZB Q0VfTU9ERV9NSUk6CisJY2FzZSBQSFlfSU5URVJGQUNFX01PREVfUk1JSToKKwljYXNlIFBIWV9J TlRFUkZBQ0VfTU9ERV9SRVZNSUk6CisJY2FzZSBQSFlfSU5URVJGQUNFX01PREVfTkE6CisJZGVm YXVsdDoKIAkJcGh5bGlua19zZXQobWFzaywgMTBiYXNlVF9IYWxmKTsKIAkJcGh5bGlua19zZXQo bWFzaywgMTBiYXNlVF9GdWxsKTsKIAkJcGh5bGlua19zZXQobWFzaywgMTAwYmFzZVRfSGFsZik7 CiAJCXBoeWxpbmtfc2V0KG1hc2ssIDEwMGJhc2VUX0Z1bGwpOworCQlicmVhazsKKwl9CiAKLQkJ aWYgKHN0YXRlLT5pbnRlcmZhY2UgIT0gUEhZX0lOVEVSRkFDRV9NT0RFX01JSSkgewotCQkJcGh5 bGlua19zZXQobWFzaywgMTAwMGJhc2VUX0hhbGYpOworCWlmIChzdGF0ZS0+aW50ZXJmYWNlID09 IFBIWV9JTlRFUkZBQ0VfTU9ERV9OQSkgeworCQlpZiAoTVRLX0hBU19DQVBTKG1hYy0+aHctPnNv Yy0+Y2FwcywgTVRLX1NHTUlJKSkgeworCQkJcGh5bGlua19zZXQobWFzaywgMTAwMGJhc2VUX0Z1 bGwpOworCQkJcGh5bGlua19zZXQobWFzaywgMTAwMGJhc2VYX0Z1bGwpOworCQkJcGh5bGlua19z ZXQobWFzaywgMjUwMGJhc2VYX0Z1bGwpOworCQl9CisJCWlmIChNVEtfSEFTX0NBUFMobWFjLT5o dy0+c29jLT5jYXBzLCBNVEtfUkdNSUkpKSB7CiAJCQlwaHlsaW5rX3NldChtYXNrLCAxMDAwYmFz ZVRfRnVsbCk7CisJCQlwaHlsaW5rX3NldChtYXNrLCAxMDAwYmFzZVRfSGFsZik7CiAJCQlwaHls aW5rX3NldChtYXNrLCAxMDAwYmFzZVhfRnVsbCk7CiAJCX0KKwkJaWYgKE1US19IQVNfQ0FQUyht YWMtPmh3LT5zb2MtPmNhcHMsIE1US19HRVBIWSkpIHsKKwkJCXBoeWxpbmtfc2V0KG1hc2ssIDEw MDBiYXNlVF9GdWxsKTsKKwkJCXBoeWxpbmtfc2V0KG1hc2ssIDEwMDBiYXNlVF9IYWxmKTsKKwkJ fQogCX0KIAogCXBoeWxpbmtfc2V0KG1hc2ssIFBhdXNlKTsKQEAgLTM5NCw2ICs1MDQsMTEgQEAg c3RhdGljIHZvaWQgbXRrX3ZhbGlkYXRlKHN0cnVjdCBwaHlsaW5rX2NvbmZpZyAqY29uZmlnLAog CiAJbGlua21vZGVfYW5kKHN1cHBvcnRlZCwgc3VwcG9ydGVkLCBtYXNrKTsKIAlsaW5rbW9kZV9h bmQoc3RhdGUtPmFkdmVydGlzaW5nLCBzdGF0ZS0+YWR2ZXJ0aXNpbmcsIG1hc2spOworCisJLyog V2UgY2FuIG9ubHkgb3BlcmF0ZSBhdCAyNTAwQmFzZVggb3IgMTAwMEJhc2VYLiBJZiByZXF1ZXN0 ZWQKKwkgKiB0byBhZHZlcnRpc2UgYm90aCwgb25seSByZXBvcnQgYWR2ZXJ0aXNpbmcgYXQgMjUw MEJhc2VYLgorCSAqLworCXBoeWxpbmtfaGVscGVyX2Jhc2V4X3NwZWVkKHN0YXRlKTsKIH0KIAog c3RhdGljIGNvbnN0IHN0cnVjdCBwaHlsaW5rX21hY19vcHMgbXRrX3BoeWxpbmtfb3BzID0gewpk aWZmIC0tZ2l0IGEvZHJpdmVycy9uZXQvZXRoZXJuZXQvbWVkaWF0ZWsvbXRrX2V0aF9zb2MuaCBi L2RyaXZlcnMvbmV0L2V0aGVybmV0L21lZGlhdGVrL210a19ldGhfc29jLmgKaW5kZXggN2Y1ZjU0 MWRhYWQ3Li43NmJkMTJjYjgxNTAgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvbmV0L2V0aGVybmV0L21l ZGlhdGVrL210a19ldGhfc29jLmgKKysrIGIvZHJpdmVycy9uZXQvZXRoZXJuZXQvbWVkaWF0ZWsv bXRrX2V0aF9zb2MuaApAQCAtNDEyLDE0ICs0MTIsMzggQEAKIC8qIFJlZ2lzdGVyIHRvIGF1dG8t bmVnb3RpYXRpb24gcmVzdGFydCAqLwogI2RlZmluZSBTR01TWVNfUENTX0NPTlRST0xfMQkweDAK ICNkZWZpbmUgU0dNSUlfQU5fUkVTVEFSVAlCSVQoOSkKKyNkZWZpbmUgU0dNSUlfSVNPTEFURQkJ QklUKDEwKQorI2RlZmluZSBTR01JSV9BTl9FTkFCTEUJCUJJVCgxMikKKyNkZWZpbmUgU0dNSUlf TElOS19TVEFUWVMJQklUKDE4KQorI2RlZmluZSBTR01JSV9BTl9BQklMSVRZCUJJVCgxOSkKKyNk ZWZpbmUgU0dNSUlfQU5fQ09NUExFVEUJQklUKDIxKQorI2RlZmluZSBTR01JSV9QQ1NfRkFVTFQJ CUJJVCgyMykKKyNkZWZpbmUgU0dNSUlfQU5fRVhQQU5TSU9OX0NMUglCSVQoMzApCiAKIC8qIFJl Z2lzdGVyIHRvIHByb2dyYW1tYWJsZSBsaW5rIHRpbWVyLCB0aGUgdW5pdCBpbiAyICogOG5zICov CiAjZGVmaW5lIFNHTVNZU19QQ1NfTElOS19USU1FUgkweDE4CiAjZGVmaW5lIFNHTUlJX0xJTktf VElNRVJfREVGQVVMVAkoMHgxODZhMCAmIEdFTk1BU0soMTksIDApKQogCiAvKiBSZWdpc3RlciB0 byBjb250cm9sIHJlbW90ZSBmYXVsdCAqLwotI2RlZmluZSBTR01TWVNfU0dNSUlfTU9ERQkweDIw Ci0jZGVmaW5lIFNHTUlJX1JFTU9URV9GQVVMVF9ESVMJQklUKDgpCisjZGVmaW5lIFNHTVNZU19T R01JSV9NT0RFCQkweDIwCisjZGVmaW5lIFNHTUlJX0lGX01PREVfQklUMAkJQklUKDApCisjZGVm aW5lIFNHTUlJX1NQRUVEX0RVUExFWF9BTgkJQklUKDEpCisjZGVmaW5lIFNHTUlJX1NQRUVEXzEw CQkJMHgwCisjZGVmaW5lIFNHTUlJX1NQRUVEXzEwMAkJCUJJVCgyKQorI2RlZmluZSBTR01JSV9T UEVFRF8xMDAwCQlCSVQoMykKKyNkZWZpbmUgU0dNSUlfRFVQTEVYX0ZVTEwJCUJJVCg0KQorI2Rl ZmluZSBTR01JSV9JRl9NT0RFX0JJVDUJCUJJVCg1KQorI2RlZmluZSBTR01JSV9SRU1PVEVfRkFV TFRfRElTCQlCSVQoOCkKKyNkZWZpbmUgU0dNSUlfQ09ERV9TWU5DX1NFVF9WQUwJCUJJVCg5KQor I2RlZmluZSBTR01JSV9DT0RFX1NZTkNfU0VUX0VOCQlCSVQoMTApCisjZGVmaW5lIFNHTUlJX1NF TkRfQU5fRVJST1JfRU4JCUJJVCgxMSkKKyNkZWZpbmUgU0dNSUlfSUZfTU9ERV9NQVNLCQlHRU5N QVNLKDUsIDEpCisKKy8qIFJlZ2lzdGVyIHRvIHNldCBTR01JSSBzcGVlZCwgQU5BIFJHXyBDb250 cm9sIFNpZ25hbHMgSUlJKi8KKyNkZWZpbmUgU0dNU1lTX0FOQV9SR19DUzMJMHgyMDI4CisjZGVm aW5lIFJHX1BIWV9TUEVFRF9NQVNLCShCSVQoMikgfCBCSVQoMykpCisjZGVmaW5lIFJHX1BIWV9T UEVFRF8xXzI1RwkweDAKKyNkZWZpbmUgUkdfUEhZX1NQRUVEXzNfMTI1RwlCSVQoMikKIAogLyog UmVnaXN0ZXIgdG8gcG93ZXIgdXAgUVBIWSAqLwogI2RlZmluZSBTR01TWVNfUVBIWV9QV1JfU1RB VEVfQ1RSTCAweGU4CkBAIC04OTcsNyArOTIxLDEyIEBAIHUzMiBtdGtfcjMyKHN0cnVjdCBtdGtf ZXRoICpldGgsIHVuc2lnbmVkIHJlZyk7CiBpbnQgbXRrX3NnbWlpX2luaXQoc3RydWN0IG10a19z Z21paSAqc3MsIHN0cnVjdCBkZXZpY2Vfbm9kZSAqbnAsCiAJCSAgIHUzMiBhbmFfcmdjMyk7CiBp bnQgbXRrX3NnbWlpX3NldHVwX21vZGVfYW4oc3RydWN0IG10a19zZ21paSAqc3MsIGludCBpZCk7 Ci1pbnQgbXRrX3NnbWlpX3NldHVwX21vZGVfZm9yY2Uoc3RydWN0IG10a19zZ21paSAqc3MsIGlu dCBpZCk7Ci1pbnQgbXRrX3NldHVwX2h3X3BhdGgoc3RydWN0IG10a19ldGggKmV0aCwgaW50IG1h Y19pZCwgaW50IHBoeW1vZGUpOworaW50IG10a19zZ21paV9zZXR1cF9tb2RlX2ZvcmNlKHN0cnVj dCBtdGtfc2dtaWkgKnNzLCBpbnQgaWQsCisJCQkgICAgICAgY29uc3Qgc3RydWN0IHBoeWxpbmtf bGlua19zdGF0ZSAqc3RhdGUpOwordm9pZCBtdGtfc2dtaWlfcmVzdGFydF9hbihzdHJ1Y3QgbXRr X2V0aCAqZXRoLCBpbnQgbWFjX2lkKTsKKworaW50IG10a19nbWFjX3NnbWlpX3BhdGhfc2V0dXAo c3RydWN0IG10a19ldGggKmV0aCwgaW50IG1hY19pZCk7CitpbnQgbXRrX2dtYWNfZ2VwaHlfcGF0 aF9zZXR1cChzdHJ1Y3QgbXRrX2V0aCAqZXRoLCBpbnQgbWFjX2lkKTsKK2ludCBtdGtfZ21hY19y Z21paV9wYXRoX3NldHVwKHN0cnVjdCBtdGtfZXRoICpldGgsIGludCBtYWNfaWQpOwogCiAjZW5k aWYgLyogTVRLX0VUSF9IICovCmRpZmYgLS1naXQgYS9kcml2ZXJzL25ldC9ldGhlcm5ldC9tZWRp YXRlay9tdGtfc2dtaWkuYyBiL2RyaXZlcnMvbmV0L2V0aGVybmV0L21lZGlhdGVrL210a19zZ21p aS5jCmluZGV4IGZmNTA5ZDQyZDgxOC4uNGRiMjdkZmM3ZWMxIDEwMDY0NAotLS0gYS9kcml2ZXJz L25ldC9ldGhlcm5ldC9tZWRpYXRlay9tdGtfc2dtaWkuYworKysgYi9kcml2ZXJzL25ldC9ldGhl cm5ldC9tZWRpYXRlay9tdGtfc2dtaWkuYwpAQCAtMTYsOCArMTYsNyBAQAogaW50IG10a19zZ21p aV9pbml0KHN0cnVjdCBtdGtfc2dtaWkgKnNzLCBzdHJ1Y3QgZGV2aWNlX25vZGUgKnIsIHUzMiBh bmFfcmdjMykKIHsKIAlzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wOwotCWNvbnN0IGNoYXIgKnN0cjsK LQlpbnQgaSwgZXJyOworCWludCBpOwogCiAJc3MtPmFuYV9yZ2MzID0gYW5hX3JnYzM7CiAKQEAg LTI5LDE5ICsyOCw2IEBAIGludCBtdGtfc2dtaWlfaW5pdChzdHJ1Y3QgbXRrX3NnbWlpICpzcywg c3RydWN0IGRldmljZV9ub2RlICpyLCB1MzIgYW5hX3JnYzMpCiAJCXNzLT5yZWdtYXBbaV0gPSBz eXNjb25fbm9kZV90b19yZWdtYXAobnApOwogCQlpZiAoSVNfRVJSKHNzLT5yZWdtYXBbaV0pKQog CQkJcmV0dXJuIFBUUl9FUlIoc3MtPnJlZ21hcFtpXSk7Ci0KLQkJZXJyID0gb2ZfcHJvcGVydHlf cmVhZF9zdHJpbmcobnAsICJtZWRpYXRlayxwaHlzcGVlZCIsICZzdHIpOwotCQlpZiAoZXJyKQot CQkJcmV0dXJuIGVycjsKLQotCQlpZiAoIXN0cmNtcChzdHIsICIyNTAwIikpCi0JCQlzcy0+Zmxh Z3NbaV0gfD0gTVRLX1NHTUlJX1BIWVNQRUVEXzI1MDA7Ci0JCWVsc2UgaWYgKCFzdHJjbXAoc3Ry LCAiMTAwMCIpKQotCQkJc3MtPmZsYWdzW2ldIHw9IE1US19TR01JSV9QSFlTUEVFRF8xMDAwOwot CQllbHNlIGlmICghc3RyY21wKHN0ciwgImF1dG8iKSkKLQkJCXNzLT5mbGFnc1tpXSB8PSBNVEtf U0dNSUlfUEhZU1BFRURfQU47Ci0JCWVsc2UKLQkJCXJldHVybiAtRUlOVkFMOwogCX0KIAogCXJl dHVybiAwOwpAQCAtNzMsMjcgKzU5LDQ1IEBAIGludCBtdGtfc2dtaWlfc2V0dXBfbW9kZV9hbihz dHJ1Y3QgbXRrX3NnbWlpICpzcywgaW50IGlkKQogCXJldHVybiAwOwogfQogCi1pbnQgbXRrX3Nn bWlpX3NldHVwX21vZGVfZm9yY2Uoc3RydWN0IG10a19zZ21paSAqc3MsIGludCBpZCkKK2ludCBt dGtfc2dtaWlfc2V0dXBfbW9kZV9mb3JjZShzdHJ1Y3QgbXRrX3NnbWlpICpzcywgaW50IGlkLAor CQkJICAgICAgIGNvbnN0IHN0cnVjdCBwaHlsaW5rX2xpbmtfc3RhdGUgKnN0YXRlKQogewogCXVu c2lnbmVkIGludCB2YWw7Ci0JaW50IG1vZGU7CiAKIAlpZiAoIXNzLT5yZWdtYXBbaWRdKQogCQly ZXR1cm4gLUVJTlZBTDsKIAogCXJlZ21hcF9yZWFkKHNzLT5yZWdtYXBbaWRdLCBzcy0+YW5hX3Jn YzMsICZ2YWwpOwotCXZhbCAmPSB+R0VOTUFTSygzLCAyKTsKLQltb2RlID0gc3MtPmZsYWdzW2lk XSAmIE1US19TR01JSV9QSFlTUEVFRF9NQVNLOwotCXZhbCB8PSAobW9kZSA9PSBNVEtfU0dNSUlf UEhZU1BFRURfMTAwMCkgPyAwIDogQklUKDIpOworCXZhbCAmPSB+UkdfUEhZX1NQRUVEX01BU0s7 CisJaWYgKHN0YXRlLT5pbnRlcmZhY2UgPT0gUEhZX0lOVEVSRkFDRV9NT0RFXzI1MDBCQVNFWCkK KwkJdmFsIHw9IFJHX1BIWV9TUEVFRF8zXzEyNUc7CiAJcmVnbWFwX3dyaXRlKHNzLT5yZWdtYXBb aWRdLCBzcy0+YW5hX3JnYzMsIHZhbCk7CiAKIAkvKiBEaXNhYmxlIFNHTUlJIEFOICovCiAJcmVn bWFwX3JlYWQoc3MtPnJlZ21hcFtpZF0sIFNHTVNZU19QQ1NfQ09OVFJPTF8xLCAmdmFsKTsKLQl2 YWwgJj0gfkJJVCgxMik7CisJdmFsICY9IH5TR01JSV9BTl9FTkFCTEU7CiAJcmVnbWFwX3dyaXRl KHNzLT5yZWdtYXBbaWRdLCBTR01TWVNfUENTX0NPTlRST0xfMSwgdmFsKTsKIAogCS8qIFNHTUlJ IGZvcmNlIG1vZGUgc2V0dGluZyAqLwotCXZhbCA9IDB4MzExMjAwMTk7CisJcmVnbWFwX3JlYWQo c3MtPnJlZ21hcFtpZF0sIFNHTVNZU19TR01JSV9NT0RFLCAmdmFsKTsKKwl2YWwgJj0gflNHTUlJ X0lGX01PREVfTUFTSzsKKworCXN3aXRjaCAoc3RhdGUtPnNwZWVkKSB7CisJY2FzZSBTUEVFRF8x MDoKKwkJdmFsIHw9IFNHTUlJX1NQRUVEXzEwOworCQlicmVhazsKKwljYXNlIFNQRUVEXzEwMDoK KwkJdmFsIHw9IFNHTUlJX1NQRUVEXzEwMDsKKwkJYnJlYWs7CisJY2FzZSBTUEVFRF8yNTAwOgor CWNhc2UgU1BFRURfMTAwMDoKKwkJdmFsIHw9IFNHTUlJX1NQRUVEXzEwMDA7CisJCWJyZWFrOwor CX07CisKKwlpZiAoc3RhdGUtPmR1cGxleCA9PSBEVVBMRVhfRlVMTCkKKwkJdmFsIHw9IFNHTUlJ X0RVUExFWF9GVUxMOworCiAJcmVnbWFwX3dyaXRlKHNzLT5yZWdtYXBbaWRdLCBTR01TWVNfU0dN SUlfTU9ERSwgdmFsKTsKIAogCS8qIFJlbGVhc2UgUEhZQSBwb3dlciBkb3duIHN0YXRlICovCkBA IC0xMDMsMyArMTA3LDIwIEBAIGludCBtdGtfc2dtaWlfc2V0dXBfbW9kZV9mb3JjZShzdHJ1Y3Qg bXRrX3NnbWlpICpzcywgaW50IGlkKQogCiAJcmV0dXJuIDA7CiB9CisKK3ZvaWQgbXRrX3NnbWlp X3Jlc3RhcnRfYW4oc3RydWN0IG10a19ldGggKmV0aCwgaW50IG1hY19pZCkKK3sKKwlzdHJ1Y3Qg bXRrX3NnbWlpICpzcyA9IGV0aC0+c2dtaWk7CisJdW5zaWduZWQgaW50IHZhbCwgc2lkOworCisJ LyogRGVjaWRlIGhvdyBHTUFDIGFuZCBTR01JSVNZUyBiZSBtYXBwZWQgKi8KKwlzaWQgPSAoTVRL X0hBU19DQVBTKGV0aC0+c29jLT5jYXBzLCBNVEtfU0hBUkVEX1NHTUlJKSkgPworCSAgICAgICAw IDogbWFjX2lkOworCisJaWYgKCFzcy0+cmVnbWFwW3NpZF0pCisJCXJldHVybjsKKworCXJlZ21h cF9yZWFkKHNzLT5yZWdtYXBbc2lkXSwgU0dNU1lTX1BDU19DT05UUk9MXzEsICZ2YWwpOworCXZh bCB8PSBTR01JSV9BTl9SRVNUQVJUOworCXJlZ21hcF93cml0ZShzcy0+cmVnbWFwW3NpZF0sIFNH TVNZU19QQ1NfQ09OVFJPTF8xLCB2YWwpOworfQotLSAKMi4yMC4xCgoKX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5n IGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5p bmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=