Re: [PATCH 4/5] x86/intel: Aggregate microserver naming

[Ingo Molnar <mingo@kernel.org>]

* Peter Zijlstra <peterz@infradead.org> wrote:

> Currently big microservers have _XEON_D while small microservers have
> _X, Make it uniformly: _D.
> 
> for i in `git grep -l "INTEL_FAM6_.*_\(X\|XEON_D\)"`
> do
> 	sed -i -e 's/\(INTEL_FAM6_ATOM_.*\)_X/\1_D/g' \
>                -e 's/\(INTEL_FAM6_.*\)_XEON_D/\1_D/g' ${i}
> done
> 
> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
> Cc: x86@kernel.org
> Cc: Dave Hansen <dave.hansen@intel.com>
> Cc: Borislav Petkov <bp@alien8.de>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Tony Luck <tony.luck@intel.com>
> ---
>  arch/x86/events/intel/core.c          |   20 ++++++++++----------
>  arch/x86/events/intel/cstate.c        |   12 ++++++------
>  arch/x86/events/intel/pt.c            |    2 +-
>  arch/x86/events/intel/rapl.c          |    4 ++--
>  arch/x86/events/intel/uncore.c        |    4 ++--
>  arch/x86/events/msr.c                 |    6 +++---
>  arch/x86/include/asm/intel-family.h   |   10 +++++-----
>  arch/x86/kernel/apic/apic.c           |    2 +-
>  arch/x86/kernel/cpu/intel.c           |    4 ++--
>  arch/x86/kernel/cpu/mce/intel.c       |    2 +-
>  arch/x86/kernel/tsc.c                 |    2 +-
>  drivers/cpufreq/intel_pstate.c        |    6 +++---
>  drivers/edac/i10nm_base.c             |    4 ++--
>  drivers/edac/pnd2_edac.c              |    2 +-
>  tools/power/x86/turbostat/turbostat.c |   22 +++++++++++-----------
>  15 files changed, 51 insertions(+), 51 deletions(-)

I've added the additional renames below, accounting for recent changes in 
cpu/common.c.

Thanks,

	Ingo

---
 arch/x86/kernel/cpu/common.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index f125bf7ecb6f..b6a9e27755d7 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1050,7 +1050,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
 	VULNWL_INTEL(ATOM_BONNELL_MID,		NO_SPECULATION),
 
 	VULNWL_INTEL(ATOM_SILVERMONT,		NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
-	VULNWL_INTEL(ATOM_SILVERMONT_X,		NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
+	VULNWL_INTEL(ATOM_SILVERMONT_D,		NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
 	VULNWL_INTEL(ATOM_SILVERMONT_MID,	NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
 	VULNWL_INTEL(ATOM_AIRMONT,		NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
 	VULNWL_INTEL(XEON_PHI_KNL,		NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
@@ -1061,7 +1061,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
 	VULNWL_INTEL(ATOM_AIRMONT_MID,		NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
 
 	VULNWL_INTEL(ATOM_GOLDMONT,		NO_MDS | NO_L1TF | NO_SWAPGS),
-	VULNWL_INTEL(ATOM_GOLDMONT_X,		NO_MDS | NO_L1TF | NO_SWAPGS),
+	VULNWL_INTEL(ATOM_GOLDMONT_D,		NO_MDS | NO_L1TF | NO_SWAPGS),
 	VULNWL_INTEL(ATOM_GOLDMONT_PLUS,	NO_MDS | NO_L1TF | NO_SWAPGS),
 
 	/*