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From: Jean Delvare <jdelvare-l3A5Bk7waGM@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: "Alex Deucher" <alexander.deucher-5C7GfCeVMHo@public.gmane.org>,
	"Ken Wang" <Qingqing.Wang-5C7GfCeVMHo@public.gmane.org>,
	"Christian König" <christian.koenig-5C7GfCeVMHo@public.gmane.org>,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	"David (ChunMing) Zhou"
	<David1.Zhou-5C7GfCeVMHo@public.gmane.org>
Subject: [PATCH] drm/amdgpu/si: fix ASIC tests
Date: Wed, 28 Aug 2019 17:05:57 +0200	[thread overview]
Message-ID: <20190828170557.37df0d7a@endymion> (raw)

Comparing adev->family with CHIP constants is not correct.
adev->family can only be compared with AMDGPU_FAMILY constants and
adev->asic_type is the struct member to compare with CHIP constants.
They are separate identification spaces.

Signed-off-by: Jean Delvare <jdelvare@suse.de>
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang <Qingqing.Wang@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: "David (ChunMing) Zhou" <David1.Zhou@amd.com>
---
I stumbled upon this while reading the code. The comparisons look
obviously incorrect, but on the other hand it's hard to believe that
the bug has been there for almost 4 years without any user reporting
any actual problem caused by it. So this probably requires a more
in-depth analysis by someone familiar with the code.

I tested these changes on my Oland card and did not notice any
difference, but I don't know what I should be looking at.

 drivers/gpu/drm/amd/amdgpu/si.c |    6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

--- linux-5.2.orig/drivers/gpu/drm/amd/amdgpu/si.c	2019-07-08 00:41:56.000000000 +0200
+++ linux-5.2/drivers/gpu/drm/amd/amdgpu/si.c	2019-08-28 10:29:43.544180131 +0200
@@ -1867,7 +1867,7 @@ static void si_program_aspm(struct amdgp
 			if (orig != data)
 				si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
 
-			if ((adev->family != CHIP_OLAND) && (adev->family != CHIP_HAINAN)) {
+			if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) {
 				orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
 				data &= ~PLL_RAMP_UP_TIME_0_MASK;
 				if (orig != data)
@@ -1916,14 +1916,14 @@ static void si_program_aspm(struct amdgp
 
 			orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
 			data &= ~LS2_EXIT_TIME_MASK;
-			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
+			if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))
 				data |= LS2_EXIT_TIME(5);
 			if (orig != data)
 				si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
 
 			orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
 			data &= ~LS2_EXIT_TIME_MASK;
-			if ((adev->family == CHIP_OLAND) || (adev->family == CHIP_HAINAN))
+			if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))
 				data |= LS2_EXIT_TIME(5);
 			if (orig != data)
 				si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);


-- 
Jean Delvare
SUSE L3 Support
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

             reply	other threads:[~2019-08-28 15:05 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-28 15:05 Jean Delvare [this message]
2019-08-28 20:28 ` [PATCH] drm/amdgpu/si: fix ASIC tests Alex Deucher

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