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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 3/7] drm/i915: protect access to DP_TP_* on non-dp
Date: Thu, 29 Aug 2019 13:37:55 +0300	[thread overview]
Message-ID: <20190829103754.GN7482@intel.com> (raw)
In-Reply-To: <20190829092554.32198-4-lucas.demarchi@intel.com>

On Thu, Aug 29, 2019 at 02:25:50AM -0700, Lucas De Marchi wrote:
> DP_TP_{CTL,STATUS} should only be programmed when the encoder is intel_dp.
> Checking its current usages intel_disable_ddi_buf() is the only
> offender, with other places being protected by checks like
> pipe_config->fec_enable that is only set by intel_dp.
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 3180dacb5be4..df3e4fe7e3e9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3462,10 +3462,12 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
>  		wait = true;
>  	}
>  
> -	val = I915_READ(DP_TP_CTL(port));
> -	val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> -	val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> -	I915_WRITE(DP_TP_CTL(port), val);
> +	if (intel_encoder_is_dp(encoder)) {

Doesn't really make sense to me. Either we just do it (because a DDI is
just a DDI so DP_TP_CTL does exist always), or we only do it when driving
DP and not when driving HDMI.

For the latter I would perhaps suggest moving all this extra junk out
from intel_disable_ddi_buf() into the DP specific code paths, leaving
just the actual DDI_BUF_CTL disable here.

> +		val = I915_READ(DP_TP_CTL(port));
> +		val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> +		val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> +		I915_WRITE(DP_TP_CTL(port), val);
> +	}
>  
>  	/* Disable FEC in DP Sink */
>  	intel_ddi_disable_fec_state(encoder, crtc_state);
> -- 
> 2.23.0

-- 
Ville Syrjälä
Intel
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  reply	other threads:[~2019-08-29 10:37 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-29  9:25 [PATCH v3 0/7] Tiger Lake batch 3.5 Lucas De Marchi
2019-08-29  9:25 ` [PATCH v3 1/7] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-09-03 21:42   ` Matt Roper
2019-09-03 21:53     ` Souza, Jose
2019-09-03 21:59       ` Matt Roper
2019-08-29  9:25 ` [PATCH v3 2/7] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-09-03 16:52   ` Matt Roper
2019-08-29  9:25 ` [PATCH v3 3/7] drm/i915: protect access to DP_TP_* on non-dp Lucas De Marchi
2019-08-29 10:37   ` Ville Syrjälä [this message]
2019-09-03 17:16     ` Matt Roper
2019-09-04  0:45       ` Souza, Jose
2019-09-04 14:14         ` Ville Syrjälä
2019-08-29  9:25 ` [PATCH v3 4/7] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
2019-09-03 17:55   ` Matt Roper
2019-09-04 20:44     ` Souza, Jose
2019-09-04 21:04       ` Souza, Jose
2019-08-29  9:25 ` [PATCH v3 5/7] drm/i915/tgl: disable SAGV temporarily Lucas De Marchi
2019-08-30 20:01   ` Souza, Jose
2019-09-03 22:05   ` Matt Roper
2019-09-03 22:45     ` Souza, Jose
2019-08-29  9:25 ` [PATCH v3 6/7] drm/i915/tgl: add gen12 to stolen initialization Lucas De Marchi
2019-09-03 21:43   ` Souza, Jose
2019-09-03 22:10   ` Matt Roper
2019-08-29  9:25 ` [PATCH v3 7/7] FIXME: drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-29  9:59 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3.5 Patchwork
2019-08-29 12:18 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-29 15:08 ` [PATCH v3 0/7] " Daniele Ceraolo Spurio
2019-08-29 23:38 ` ✓ Fi.CI.IGT: success for " Patchwork

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