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ESMTP id D92D44A4F7 for ; Thu, 5 Sep 2019 12:02:54 -0400 (EDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 577AE28; Thu, 5 Sep 2019 09:02:54 -0700 (PDT) Received: from filthy-habits.cambridge.arm.com (filthy-habits.cambridge.arm.com [10.1.197.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DB2923F67D; Thu, 5 Sep 2019 09:02:52 -0700 (PDT) From: Marc Zyngier To: Peter Maydell , James Morse , Julien Thierry , Suzuki K Poulose , Zenghui Yu , Will Deacon , Eric Auger Subject: [PATCH v2] KVM: arm/arm64: vgic: Allow more than 256 vcpus for KVM_IRQ_LINE Date: Thu, 5 Sep 2019 17:02:45 +0100 Message-Id: <20190905160245.20746-1-maz@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Cc: qemu-arm@nongnu.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list 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IG9ubHkgNCBiaXRzLCBhbmQgYWxsb2NhdGUgdGhlCnJlbWFpbmluZyA0IGJpdHMgdG8gYSB2Y3B1 Ml9pbmRleCwgd2hpY2ggYWN0cyBhcyBhIG11bHRpcGxpZXI6CgogIHZjcHVfaWQgPSAyNTYgKiB2 Y3B1Ml9pbmRleCArIHZjcHVfaW5kZXgKCldpdGggdGhhdCwgYW5kIGEgbmV3IGNhcGFiaWxpdHkg KEtWTV9DQVBfQVJNX0lSUV9MSU5FX0xBWU9VVF8yKQphbGxvd2luZyB0aGlzIHRvIGJlIGRpc2Nv dmVyZWQsIGl0IGJlY29tZXMgcG9zc2libGUgdG8gaW5qZWN0ClBQSXMgdG8gdXAgdG8gNDA5NiB2 Y3B1cy4gQnV0IHBsZWFzZSBqdXN0IGRvbid0LgoKV2hpbHN0IHdlJ3JlIHRoZXJlLCBhZGQgYSBj bGFyaWZpY2F0aW9uIGFib3V0IHRoZSB1c2Ugb2YgS1ZNX0lSUV9MSU5FCm9uIGFybSwgd2hpY2gg aXMgbm90IGNvbXBsZXRlbHkgY29uZGl0aW9ubmVkIGJ5IEtWTV9DQVBfSVJRQ0hJUC4KClJlcG9y dGVkLWJ5OiBaZW5naHVpIFl1IDx5dXplbmdodWlAaHVhd2VpLmNvbT4KUmV2aWV3ZWQtYnk6IEVy aWMgQXVnZXIgPGVyaWMuYXVnZXJAcmVkaGF0LmNvbT4KUmV2aWV3ZWQtYnk6IFplbmdodWkgWXUg PHl1emVuZ2h1aUBodWF3ZWkuY29tPgpTaWduZWQtb2ZmLWJ5OiBNYXJjIFp5bmdpZXIgPG1hekBr ZXJuZWwub3JnPgotLS0KKiBGcm9tIHYxIChodHRwczovL2xvcmUua2VybmVsLm9yZy9yLzIwMTkw ODE4MTQwNzEwLjIzOTIwLTEtbWF6QGtlcm5lbC5vcmcpCiAgLSBBbHdheXMgc2F5IHRoYXQgd2Ug c3VwcG9ydCB0aGUgbmV3IGxheW91dCwgbm8gbWF0dGVyIHdoZXRoZXIKICAgIHdlIGhhdmUgYW4g aW4ta2VybmVsIGlycWNoaXAgb3Igbm90CiAgLSBDbGFyaWZ5IHVzZSBvZiBLVk1fSVJRX0xJTkUg d3J0IEtWTV9DQVBfSVJRQ0hJUAogIC0gQ29sbGVjdGVkIFJCcwoKIERvY3VtZW50YXRpb24vdmly dC9rdm0vYXBpLnR4dCAgICB8IDEyICsrKysrKysrKystLQogYXJjaC9hcm0vaW5jbHVkZS91YXBp L2FzbS9rdm0uaCAgIHwgIDQgKysrLQogYXJjaC9hcm02NC9pbmNsdWRlL3VhcGkvYXNtL2t2bS5o IHwgIDQgKysrLQogaW5jbHVkZS91YXBpL2xpbnV4L2t2bS5oICAgICAgICAgIHwgIDEgKwogdmly dC9rdm0vYXJtL2FybS5jICAgICAgICAgICAgICAgIHwgIDIgKysKIDUgZmlsZXMgY2hhbmdlZCwg MTkgaW5zZXJ0aW9ucygrKSwgNCBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9Eb2N1bWVudGF0 aW9uL3ZpcnQva3ZtL2FwaS50eHQgYi9Eb2N1bWVudGF0aW9uL3ZpcnQva3ZtL2FwaS50eHQKaW5k ZXggMmQwNjc3NjdiNjE3Li4yNTkzMWNhMWNiMzggMTAwNjQ0Ci0tLSBhL0RvY3VtZW50YXRpb24v dmlydC9rdm0vYXBpLnR4dAorKysgYi9Eb2N1bWVudGF0aW9uL3ZpcnQva3ZtL2FwaS50eHQKQEAg LTc1Myw4ICs3NTMsOCBAQCBpbi1rZXJuZWwgaXJxY2hpcCAoR0lDKSwgYW5kIGZvciBpbi1rZXJu ZWwgaXJxY2hpcCBjYW4gdGVsbCB0aGUgR0lDIHRvCiB1c2UgUFBJcyBkZXNpZ25hdGVkIGZvciBz cGVjaWZpYyBjcHVzLiAgVGhlIGlycSBmaWVsZCBpcyBpbnRlcnByZXRlZAogbGlrZSB0aGlzOgog Ci0gwqBiaXRzOiAgfCAzMSAuLi4gMjQgfCAyMyAgLi4uIDE2IHwgMTUgICAgLi4uICAgIDAgfAot ICBmaWVsZDogfCBpcnFfdHlwZSAgfCB2Y3B1X2luZGV4IHwgICAgIGlycV9pZCAgICAgfAorIMKg Yml0czogIHwgIDMxIC4uLiAyOCAgfCAyNyAuLi4gMjQgfCAyMyAgLi4uIDE2IHwgMTUgLi4uIDAg fAorICBmaWVsZDogfCB2Y3B1Ml9pbmRleCB8IGlycV90eXBlICB8IHZjcHVfaW5kZXggfCAgaXJx X2lkICB8CiAKIFRoZSBpcnFfdHlwZSBmaWVsZCBoYXMgdGhlIGZvbGxvd2luZyB2YWx1ZXM6CiAt IGlycV90eXBlWzBdOiBvdXQtb2Yta2VybmVsIEdJQzogaXJxX2lkIDAgaXMgSVJRLCBpcnFfaWQg MSBpcyBGSVEKQEAgLTc2Niw2ICs3NjYsMTQgQEAgVGhlIGlycV90eXBlIGZpZWxkIGhhcyB0aGUg Zm9sbG93aW5nIHZhbHVlczoKIAogSW4gYm90aCBjYXNlcywgbGV2ZWwgaXMgdXNlZCB0byBhc3Nl cnQvZGVhc3NlcnQgdGhlIGxpbmUuCiAKK1doZW4gS1ZNX0NBUF9BUk1fSVJRX0xJTkVfTEFZT1VU XzIgaXMgc3VwcG9ydGVkLCB0aGUgdGFyZ2V0IHZjcHUgaXMKK2lkZW50aWZpZWQgYXMgKDI1NiAq IHZjcHUyX2luZGV4ICsgdmNwdV9pbmRleCkuIE90aGVyd2lzZSwgdmNwdTJfaW5kZXgKK211c3Qg YmUgemVyby4KKworTm90ZSB0aGF0IG9uIGFybS9hcm02NCwgdGhlIEtWTV9DQVBfSVJRQ0hJUCBj YXBhYmlsaXR5IG9ubHkgY29uZGl0aW9ucworaW5qZWN0aW9uIG9mIGludGVycnVwdHMgZm9yIHRo ZSBpbi1rZXJuZWwgaXJxY2hpcC4gS1ZNX0lSUV9MSU5FIGNhbiBhbHdheXMKK2JlIHVzZWQgZm9y IGEgdXNlcnNwYWNlIGludGVycnVwdCBjb250cm9sbGVyLgorCiBzdHJ1Y3Qga3ZtX2lycV9sZXZl bCB7CiAJdW5pb24gewogCQlfX3UzMiBpcnE7ICAgICAvKiBHU0kgKi8KZGlmZiAtLWdpdCBhL2Fy Y2gvYXJtL2luY2x1ZGUvdWFwaS9hc20va3ZtLmggYi9hcmNoL2FybS9pbmNsdWRlL3VhcGkvYXNt L2t2bS5oCmluZGV4IGE0MjE3YzFhNWQwMS4uMjc2OTM2MGYxOTVjIDEwMDY0NAotLS0gYS9hcmNo L2FybS9pbmNsdWRlL3VhcGkvYXNtL2t2bS5oCisrKyBiL2FyY2gvYXJtL2luY2x1ZGUvdWFwaS9h c20va3ZtLmgKQEAgLTI2Niw4ICsyNjYsMTAgQEAgc3RydWN0IGt2bV92Y3B1X2V2ZW50cyB7CiAj ZGVmaW5lICAgS1ZNX0RFVl9BUk1fSVRTX0NUUkxfUkVTRVQJCTQKIAogLyogS1ZNX0lSUV9MSU5F IGlycSBmaWVsZCBpbmRleCB2YWx1ZXMgKi8KKyNkZWZpbmUgS1ZNX0FSTV9JUlFfVkNQVTJfU0hJ RlQJCTI4CisjZGVmaW5lIEtWTV9BUk1fSVJRX1ZDUFUyX01BU0sJCTB4ZgogI2RlZmluZSBLVk1f QVJNX0lSUV9UWVBFX1NISUZUCQkyNAotI2RlZmluZSBLVk1fQVJNX0lSUV9UWVBFX01BU0sJCTB4 ZmYKKyNkZWZpbmUgS1ZNX0FSTV9JUlFfVFlQRV9NQVNLCQkweGYKICNkZWZpbmUgS1ZNX0FSTV9J UlFfVkNQVV9TSElGVAkJMTYKICNkZWZpbmUgS1ZNX0FSTV9JUlFfVkNQVV9NQVNLCQkweGZmCiAj ZGVmaW5lIEtWTV9BUk1fSVJRX05VTV9TSElGVAkJMApkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9p bmNsdWRlL3VhcGkvYXNtL2t2bS5oIGIvYXJjaC9hcm02NC9pbmNsdWRlL3VhcGkvYXNtL2t2bS5o CmluZGV4IDlhNTA3NzE2YWUyZi4uNjdjMjFmOWJkYmFkIDEwMDY0NAotLS0gYS9hcmNoL2FybTY0 L2luY2x1ZGUvdWFwaS9hc20va3ZtLmgKKysrIGIvYXJjaC9hcm02NC9pbmNsdWRlL3VhcGkvYXNt L2t2bS5oCkBAIC0zMjUsOCArMzI1LDEwIEBAIHN0cnVjdCBrdm1fdmNwdV9ldmVudHMgewogI2Rl ZmluZSAgIEtWTV9BUk1fVkNQVV9USU1FUl9JUlFfUFRJTUVSCQkxCiAKIC8qIEtWTV9JUlFfTElO RSBpcnEgZmllbGQgaW5kZXggdmFsdWVzICovCisjZGVmaW5lIEtWTV9BUk1fSVJRX1ZDUFUyX1NI SUZUCQkyOAorI2RlZmluZSBLVk1fQVJNX0lSUV9WQ1BVMl9NQVNLCQkweGYKICNkZWZpbmUgS1ZN X0FSTV9JUlFfVFlQRV9TSElGVAkJMjQKLSNkZWZpbmUgS1ZNX0FSTV9JUlFfVFlQRV9NQVNLCQkw eGZmCisjZGVmaW5lIEtWTV9BUk1fSVJRX1RZUEVfTUFTSwkJMHhmCiAjZGVmaW5lIEtWTV9BUk1f SVJRX1ZDUFVfU0hJRlQJCTE2CiAjZGVmaW5lIEtWTV9BUk1fSVJRX1ZDUFVfTUFTSwkJMHhmZgog I2RlZmluZSBLVk1fQVJNX0lSUV9OVU1fU0hJRlQJCTAKZGlmZiAtLWdpdCBhL2luY2x1ZGUvdWFw aS9saW51eC9rdm0uaCBiL2luY2x1ZGUvdWFwaS9saW51eC9rdm0uaAppbmRleCA1ZTNmMTJkNTM1 OWUuLjU0MTRiNjU4OGZiYiAxMDA2NDQKLS0tIGEvaW5jbHVkZS91YXBpL2xpbnV4L2t2bS5oCisr KyBiL2luY2x1ZGUvdWFwaS9saW51eC9rdm0uaApAQCAtOTk2LDYgKzk5Niw3IEBAIHN0cnVjdCBr dm1fcHBjX3Jlc2l6ZV9ocHQgewogI2RlZmluZSBLVk1fQ0FQX0FSTV9QVFJBVVRIX0FERFJFU1Mg MTcxCiAjZGVmaW5lIEtWTV9DQVBfQVJNX1BUUkFVVEhfR0VORVJJQyAxNzIKICNkZWZpbmUgS1ZN X0NBUF9QTVVfRVZFTlRfRklMVEVSIDE3MworI2RlZmluZSBLVk1fQ0FQX0FSTV9JUlFfTElORV9M QVlPVVRfMiAxNzQKIAogI2lmZGVmIEtWTV9DQVBfSVJRX1JPVVRJTkcKIApkaWZmIC0tZ2l0IGEv dmlydC9rdm0vYXJtL2FybS5jIGIvdmlydC9rdm0vYXJtL2FybS5jCmluZGV4IDM1YTA2OTgxNWJh Zi4uODZjNmFhMWNiNThlIDEwMDY0NAotLS0gYS92aXJ0L2t2bS9hcm0vYXJtLmMKKysrIGIvdmly dC9rdm0vYXJtL2FybS5jCkBAIC0xOTYsNiArMTk2LDcgQEAgaW50IGt2bV92bV9pb2N0bF9jaGVj a19leHRlbnNpb24oc3RydWN0IGt2bSAqa3ZtLCBsb25nIGV4dCkKIAljYXNlIEtWTV9DQVBfTVBf U1RBVEU6CiAJY2FzZSBLVk1fQ0FQX0lNTUVESUFURV9FWElUOgogCWNhc2UgS1ZNX0NBUF9WQ1BV X0VWRU5UUzoKKwljYXNlIEtWTV9DQVBfQVJNX0lSUV9MSU5FX0xBWU9VVF8yOgogCQlyID0gMTsK IAkJYnJlYWs7CiAJY2FzZSBLVk1fQ0FQX0FSTV9TRVRfREVWSUNFX0FERFI6CkBAIC04ODgsNiAr ODg5LDcgQEAgaW50IGt2bV92bV9pb2N0bF9pcnFfbGluZShzdHJ1Y3Qga3ZtICprdm0sIHN0cnVj dCBrdm1faXJxX2xldmVsICppcnFfbGV2ZWwsCiAKIAlpcnFfdHlwZSA9IChpcnEgPj4gS1ZNX0FS TV9JUlFfVFlQRV9TSElGVCkgJiBLVk1fQVJNX0lSUV9UWVBFX01BU0s7CiAJdmNwdV9pZHggPSAo aXJxID4+IEtWTV9BUk1fSVJRX1ZDUFVfU0hJRlQpICYgS1ZNX0FSTV9JUlFfVkNQVV9NQVNLOwor CXZjcHVfaWR4ICs9ICgoaXJxID4+IEtWTV9BUk1fSVJRX1ZDUFUyX1NISUZUKSAmIEtWTV9BUk1f SVJRX1ZDUFUyX01BU0spICogKEtWTV9BUk1fSVJRX1ZDUFVfTUFTSyArIDEpOwogCWlycV9udW0g PSAoaXJxID4+IEtWTV9BUk1fSVJRX05VTV9TSElGVCkgJiBLVk1fQVJNX0lSUV9OVU1fTUFTSzsK IAogCXRyYWNlX2t2bV9pcnFfbGluZShpcnFfdHlwZSwgdmNwdV9pZHgsIGlycV9udW0sIGlycV9s ZXZlbC0+bGV2ZWwpOwotLSAKMi4yMC4xCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwprdm1hcm0gbWFpbGluZyBsaXN0Cmt2bWFybUBsaXN0cy5jcy5jb2x1 bWJpYS5lZHUKaHR0cHM6Ly9saXN0cy5jcy5jb2x1bWJpYS5lZHUvbWFpbG1hbi9saXN0aW5mby9r dm1hcm0K From mboxrd@z Thu Jan 1 00:00:00 1970 Received: by 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[209.132.180.67]) by mx.google.com with ESMTP id 88si2444648plf.39.2019.09.05.09.02.56; Thu, 05 Sep 2019 09:02:56 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of kvm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of kvm-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=kvm-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389437AbfIEQCz (ORCPT + 4 others); Thu, 5 Sep 2019 12:02:55 -0400 Received: from foss.arm.com ([217.140.110.172]:47030 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730518AbfIEQCz (ORCPT ); Thu, 5 Sep 2019 12:02:55 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 577AE28; Thu, 5 Sep 2019 09:02:54 -0700 (PDT) Received: from filthy-habits.cambridge.arm.com (filthy-habits.cambridge.arm.com [10.1.197.61]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DB2923F67D; Thu, 5 Sep 2019 09:02:52 -0700 (PDT) From: Marc Zyngier To: Peter Maydell , James Morse , Julien Thierry , Suzuki K Poulose , Zenghui Yu , Will Deacon , Eric Auger Cc: qemu-arm@nongnu.org, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Subject: [PATCH v2] KVM: arm/arm64: vgic: Allow more than 256 vcpus for KVM_IRQ_LINE Date: Thu, 5 Sep 2019 17:02:45 +0100 Message-Id: <20190905160245.20746-1-maz@kernel.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-TUID: fB16jUSrpq5O While parts of the VGIC support a large number of vcpus (we bravely allow up to 512), other parts are more limited. One of these limits is visible in the KVM_IRQ_LINE ioctl, which only allows 256 vcpus to be signalled when using the CPU or PPI types. Unfortunately, we've cornered ourselves badly by allocating all the bits in the irq field. Since the irq_type subfield (8 bit wide) is currently only taking the values 0, 1 and 2 (and we have been careful not to allow anything else), let's reduce this field to only 4 bits, and allocate the remaining 4 bits to a vcpu2_index, which acts as a multiplier: vcpu_id = 256 * vcpu2_index + vcpu_index With that, and a new capability (KVM_CAP_ARM_IRQ_LINE_LAYOUT_2) allowing this to be discovered, it becomes possible to inject PPIs to up to 4096 vcpus. But please just don't. Whilst we're there, add a clarification about the use of KVM_IRQ_LINE on arm, which is not completely conditionned by KVM_CAP_IRQCHIP. Reported-by: Zenghui Yu Reviewed-by: Eric Auger Reviewed-by: Zenghui Yu Signed-off-by: Marc Zyngier --- * From v1 (https://lore.kernel.org/r/20190818140710.23920-1-maz@kernel.org) - Always say that we support the new layout, no matter whether we have an in-kernel irqchip or not - Clarify use of KVM_IRQ_LINE wrt KVM_CAP_IRQCHIP - Collected RBs Documentation/virt/kvm/api.txt | 12 ++++++++++-- arch/arm/include/uapi/asm/kvm.h | 4 +++- arch/arm64/include/uapi/asm/kvm.h | 4 +++- include/uapi/linux/kvm.h | 1 + virt/kvm/arm/arm.c | 2 ++ 5 files changed, 19 insertions(+), 4 deletions(-) diff --git a/Documentation/virt/kvm/api.txt b/Documentation/virt/kvm/api.txt index 2d067767b617..25931ca1cb38 100644 --- a/Documentation/virt/kvm/api.txt +++ b/Documentation/virt/kvm/api.txt @@ -753,8 +753,8 @@ in-kernel irqchip (GIC), and for in-kernel irqchip can tell the GIC to use PPIs designated for specific cpus. The irq field is interpreted like this: -  bits: | 31 ... 24 | 23 ... 16 | 15 ... 0 | - field: | irq_type | vcpu_index | irq_id | +  bits: | 31 ... 28 | 27 ... 24 | 23 ... 16 | 15 ... 0 | + field: | vcpu2_index | irq_type | vcpu_index | irq_id | The irq_type field has the following values: - irq_type[0]: out-of-kernel GIC: irq_id 0 is IRQ, irq_id 1 is FIQ @@ -766,6 +766,14 @@ The irq_type field has the following values: In both cases, level is used to assert/deassert the line. +When KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 is supported, the target vcpu is +identified as (256 * vcpu2_index + vcpu_index). Otherwise, vcpu2_index +must be zero. + +Note that on arm/arm64, the KVM_CAP_IRQCHIP capability only conditions +injection of interrupts for the in-kernel irqchip. KVM_IRQ_LINE can always +be used for a userspace interrupt controller. + struct kvm_irq_level { union { __u32 irq; /* GSI */ diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h index a4217c1a5d01..2769360f195c 100644 --- a/arch/arm/include/uapi/asm/kvm.h +++ b/arch/arm/include/uapi/asm/kvm.h @@ -266,8 +266,10 @@ struct kvm_vcpu_events { #define KVM_DEV_ARM_ITS_CTRL_RESET 4 /* KVM_IRQ_LINE irq field index values */ +#define KVM_ARM_IRQ_VCPU2_SHIFT 28 +#define KVM_ARM_IRQ_VCPU2_MASK 0xf #define KVM_ARM_IRQ_TYPE_SHIFT 24 -#define KVM_ARM_IRQ_TYPE_MASK 0xff +#define KVM_ARM_IRQ_TYPE_MASK 0xf #define KVM_ARM_IRQ_VCPU_SHIFT 16 #define KVM_ARM_IRQ_VCPU_MASK 0xff #define KVM_ARM_IRQ_NUM_SHIFT 0 diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 9a507716ae2f..67c21f9bdbad 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -325,8 +325,10 @@ struct kvm_vcpu_events { #define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1 /* KVM_IRQ_LINE irq field index values */ +#define KVM_ARM_IRQ_VCPU2_SHIFT 28 +#define KVM_ARM_IRQ_VCPU2_MASK 0xf #define KVM_ARM_IRQ_TYPE_SHIFT 24 -#define KVM_ARM_IRQ_TYPE_MASK 0xff +#define KVM_ARM_IRQ_TYPE_MASK 0xf #define KVM_ARM_IRQ_VCPU_SHIFT 16 #define KVM_ARM_IRQ_VCPU_MASK 0xff #define KVM_ARM_IRQ_NUM_SHIFT 0 diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h index 5e3f12d5359e..5414b6588fbb 100644 --- a/include/uapi/linux/kvm.h +++ b/include/uapi/linux/kvm.h @@ -996,6 +996,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_ARM_PTRAUTH_ADDRESS 171 #define KVM_CAP_ARM_PTRAUTH_GENERIC 172 #define KVM_CAP_PMU_EVENT_FILTER 173 +#define KVM_CAP_ARM_IRQ_LINE_LAYOUT_2 174 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c index 35a069815baf..86c6aa1cb58e 100644 --- a/virt/kvm/arm/arm.c +++ b/virt/kvm/arm/arm.c @@ -196,6 +196,7 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_MP_STATE: case KVM_CAP_IMMEDIATE_EXIT: case KVM_CAP_VCPU_EVENTS: + case KVM_CAP_ARM_IRQ_LINE_LAYOUT_2: r = 1; break; case KVM_CAP_ARM_SET_DEVICE_ADDR: @@ -888,6 +889,7 @@ int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_level, irq_type = (irq >> KVM_ARM_IRQ_TYPE_SHIFT) & KVM_ARM_IRQ_TYPE_MASK; vcpu_idx = (irq >> KVM_ARM_IRQ_VCPU_SHIFT) & KVM_ARM_IRQ_VCPU_MASK; + vcpu_idx += ((irq >> KVM_ARM_IRQ_VCPU2_SHIFT) & KVM_ARM_IRQ_VCPU2_MASK) * (KVM_ARM_IRQ_VCPU_MASK + 1); irq_num = (irq >> KVM_ARM_IRQ_NUM_SHIFT) & KVM_ARM_IRQ_NUM_MASK; trace_kvm_irq_line(irq_type, vcpu_idx, irq_num, irq_level->level); -- 2.20.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable 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c2VsdmVzIGJhZGx5IGJ5IGFsbG9jYXRpbmcKYWxsIHRoZSBiaXRzIGluIHRoZSBpcnEgZmllbGQu CgpTaW5jZSB0aGUgaXJxX3R5cGUgc3ViZmllbGQgKDggYml0IHdpZGUpIGlzIGN1cnJlbnRseSBv bmx5IHRha2luZwp0aGUgdmFsdWVzIDAsIDEgYW5kIDIgKGFuZCB3ZSBoYXZlIGJlZW4gY2FyZWZ1 bCBub3QgdG8gYWxsb3cgYW55dGhpbmcKZWxzZSksIGxldCdzIHJlZHVjZSB0aGlzIGZpZWxkIHRv IG9ubHkgNCBiaXRzLCBhbmQgYWxsb2NhdGUgdGhlCnJlbWFpbmluZyA0IGJpdHMgdG8gYSB2Y3B1 Ml9pbmRleCwgd2hpY2ggYWN0cyBhcyBhIG11bHRpcGxpZXI6CgogIHZjcHVfaWQgPSAyNTYgKiB2 Y3B1Ml9pbmRleCArIHZjcHVfaW5kZXgKCldpdGggdGhhdCwgYW5kIGEgbmV3IGNhcGFiaWxpdHkg KEtWTV9DQVBfQVJNX0lSUV9MSU5FX0xBWU9VVF8yKQphbGxvd2luZyB0aGlzIHRvIGJlIGRpc2Nv dmVyZWQsIGl0IGJlY29tZXMgcG9zc2libGUgdG8gaW5qZWN0ClBQSXMgdG8gdXAgdG8gNDA5NiB2 Y3B1cy4gQnV0IHBsZWFzZSBqdXN0IGRvbid0LgoKV2hpbHN0IHdlJ3JlIHRoZXJlLCBhZGQgYSBj bGFyaWZpY2F0aW9uIGFib3V0IHRoZSB1c2Ugb2YgS1ZNX0lSUV9MSU5FCm9uIGFybSwgd2hpY2gg aXMgbm90IGNvbXBsZXRlbHkgY29uZGl0aW9ubmVkIGJ5IEtWTV9DQVBfSVJRQ0hJUC4KClJlcG9y dGVkLWJ5OiBaZW5naHVpIFl1IDx5dXplbmdodWlAaHVhd2VpLmNvbT4KUmV2aWV3ZWQtYnk6IEVy aWMgQXVnZXIgPGVyaWMuYXVnZXJAcmVkaGF0LmNvbT4KUmV2aWV3ZWQtYnk6IFplbmdodWkgWXUg PHl1emVuZ2h1aUBodWF3ZWkuY29tPgpTaWduZWQtb2ZmLWJ5OiBNYXJjIFp5bmdpZXIgPG1hekBr ZXJuZWwub3JnPgotLS0KKiBGcm9tIHYxIChodHRwczovL2xvcmUua2VybmVsLm9yZy9yLzIwMTkw ODE4MTQwNzEwLjIzOTIwLTEtbWF6QGtlcm5lbC5vcmcpCiAgLSBBbHdheXMgc2F5IHRoYXQgd2Ug c3VwcG9ydCB0aGUgbmV3IGxheW91dCwgbm8gbWF0dGVyIHdoZXRoZXIKICAgIHdlIGhhdmUgYW4g aW4ta2VybmVsIGlycWNoaXAgb3Igbm90CiAgLSBDbGFyaWZ5IHVzZSBvZiBLVk1fSVJRX0xJTkUg d3J0IEtWTV9DQVBfSVJRQ0hJUAogIC0gQ29sbGVjdGVkIFJCcwoKIERvY3VtZW50YXRpb24vdmly dC9rdm0vYXBpLnR4dCAgICB8IDEyICsrKysrKysrKystLQogYXJjaC9hcm0vaW5jbHVkZS91YXBp L2FzbS9rdm0uaCAgIHwgIDQgKysrLQogYXJjaC9hcm02NC9pbmNsdWRlL3VhcGkvYXNtL2t2bS5o IHwgIDQgKysrLQogaW5jbHVkZS91YXBpL2xpbnV4L2t2bS5oICAgICAgICAgIHwgIDEgKwogdmly dC9rdm0vYXJtL2FybS5jICAgICAgICAgICAgICAgIHwgIDIgKysKIDUgZmlsZXMgY2hhbmdlZCwg MTkgaW5zZXJ0aW9ucygrKSwgNCBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9Eb2N1bWVudGF0 aW9uL3ZpcnQva3ZtL2FwaS50eHQgYi9Eb2N1bWVudGF0aW9uL3ZpcnQva3ZtL2FwaS50eHQKaW5k ZXggMmQwNjc3NjdiNjE3Li4yNTkzMWNhMWNiMzggMTAwNjQ0Ci0tLSBhL0RvY3VtZW50YXRpb24v dmlydC9rdm0vYXBpLnR4dAorKysgYi9Eb2N1bWVudGF0aW9uL3ZpcnQva3ZtL2FwaS50eHQKQEAg LTc1Myw4ICs3NTMsOCBAQCBpbi1rZXJuZWwgaXJxY2hpcCAoR0lDKSwgYW5kIGZvciBpbi1rZXJu ZWwgaXJxY2hpcCBjYW4gdGVsbCB0aGUgR0lDIHRvCiB1c2UgUFBJcyBkZXNpZ25hdGVkIGZvciBz cGVjaWZpYyBjcHVzLiAgVGhlIGlycSBmaWVsZCBpcyBpbnRlcnByZXRlZAogbGlrZSB0aGlzOgog Ci0gwqBiaXRzOiAgfCAzMSAuLi4gMjQgfCAyMyAgLi4uIDE2IHwgMTUgICAgLi4uICAgIDAgfAot ICBmaWVsZDogfCBpcnFfdHlwZSAgfCB2Y3B1X2luZGV4IHwgICAgIGlycV9pZCAgICAgfAorIMKg Yml0czogIHwgIDMxIC4uLiAyOCAgfCAyNyAuLi4gMjQgfCAyMyAgLi4uIDE2IHwgMTUgLi4uIDAg fAorICBmaWVsZDogfCB2Y3B1Ml9pbmRleCB8IGlycV90eXBlICB8IHZjcHVfaW5kZXggfCAgaXJx X2lkICB8CiAKIFRoZSBpcnFfdHlwZSBmaWVsZCBoYXMgdGhlIGZvbGxvd2luZyB2YWx1ZXM6CiAt IGlycV90eXBlWzBdOiBvdXQtb2Yta2VybmVsIEdJQzogaXJxX2lkIDAgaXMgSVJRLCBpcnFfaWQg MSBpcyBGSVEKQEAgLTc2Niw2ICs3NjYsMTQgQEAgVGhlIGlycV90eXBlIGZpZWxkIGhhcyB0aGUg Zm9sbG93aW5nIHZhbHVlczoKIAogSW4gYm90aCBjYXNlcywgbGV2ZWwgaXMgdXNlZCB0byBhc3Nl cnQvZGVhc3NlcnQgdGhlIGxpbmUuCiAKK1doZW4gS1ZNX0NBUF9BUk1fSVJRX0xJTkVfTEFZT1VU XzIgaXMgc3VwcG9ydGVkLCB0aGUgdGFyZ2V0IHZjcHUgaXMKK2lkZW50aWZpZWQgYXMgKDI1NiAq IHZjcHUyX2luZGV4ICsgdmNwdV9pbmRleCkuIE90aGVyd2lzZSwgdmNwdTJfaW5kZXgKK211c3Qg YmUgemVyby4KKworTm90ZSB0aGF0IG9uIGFybS9hcm02NCwgdGhlIEtWTV9DQVBfSVJRQ0hJUCBj YXBhYmlsaXR5IG9ubHkgY29uZGl0aW9ucworaW5qZWN0aW9uIG9mIGludGVycnVwdHMgZm9yIHRo ZSBpbi1rZXJuZWwgaXJxY2hpcC4gS1ZNX0lSUV9MSU5FIGNhbiBhbHdheXMKK2JlIHVzZWQgZm9y IGEgdXNlcnNwYWNlIGludGVycnVwdCBjb250cm9sbGVyLgorCiBzdHJ1Y3Qga3ZtX2lycV9sZXZl bCB7CiAJdW5pb24gewogCQlfX3UzMiBpcnE7ICAgICAvKiBHU0kgKi8KZGlmZiAtLWdpdCBhL2Fy Y2gvYXJtL2luY2x1ZGUvdWFwaS9hc20va3ZtLmggYi9hcmNoL2FybS9pbmNsdWRlL3VhcGkvYXNt L2t2bS5oCmluZGV4IGE0MjE3YzFhNWQwMS4uMjc2OTM2MGYxOTVjIDEwMDY0NAotLS0gYS9hcmNo L2FybS9pbmNsdWRlL3VhcGkvYXNtL2t2bS5oCisrKyBiL2FyY2gvYXJtL2luY2x1ZGUvdWFwaS9h c20va3ZtLmgKQEAgLTI2Niw4ICsyNjYsMTAgQEAgc3RydWN0IGt2bV92Y3B1X2V2ZW50cyB7CiAj ZGVmaW5lICAgS1ZNX0RFVl9BUk1fSVRTX0NUUkxfUkVTRVQJCTQKIAogLyogS1ZNX0lSUV9MSU5F IGlycSBmaWVsZCBpbmRleCB2YWx1ZXMgKi8KKyNkZWZpbmUgS1ZNX0FSTV9JUlFfVkNQVTJfU0hJ RlQJCTI4CisjZGVmaW5lIEtWTV9BUk1fSVJRX1ZDUFUyX01BU0sJCTB4ZgogI2RlZmluZSBLVk1f QVJNX0lSUV9UWVBFX1NISUZUCQkyNAotI2RlZmluZSBLVk1fQVJNX0lSUV9UWVBFX01BU0sJCTB4 ZmYKKyNkZWZpbmUgS1ZNX0FSTV9JUlFfVFlQRV9NQVNLCQkweGYKICNkZWZpbmUgS1ZNX0FSTV9J UlFfVkNQVV9TSElGVAkJMTYKICNkZWZpbmUgS1ZNX0FSTV9JUlFfVkNQVV9NQVNLCQkweGZmCiAj ZGVmaW5lIEtWTV9BUk1fSVJRX05VTV9TSElGVAkJMApkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9p bmNsdWRlL3VhcGkvYXNtL2t2bS5oIGIvYXJjaC9hcm02NC9pbmNsdWRlL3VhcGkvYXNtL2t2bS5o CmluZGV4IDlhNTA3NzE2YWUyZi4uNjdjMjFmOWJkYmFkIDEwMDY0NAotLS0gYS9hcmNoL2FybTY0 L2luY2x1ZGUvdWFwaS9hc20va3ZtLmgKKysrIGIvYXJjaC9hcm02NC9pbmNsdWRlL3VhcGkvYXNt L2t2bS5oCkBAIC0zMjUsOCArMzI1LDEwIEBAIHN0cnVjdCBrdm1fdmNwdV9ldmVudHMgewogI2Rl ZmluZSAgIEtWTV9BUk1fVkNQVV9USU1FUl9JUlFfUFRJTUVSCQkxCiAKIC8qIEtWTV9JUlFfTElO RSBpcnEgZmllbGQgaW5kZXggdmFsdWVzICovCisjZGVmaW5lIEtWTV9BUk1fSVJRX1ZDUFUyX1NI SUZUCQkyOAorI2RlZmluZSBLVk1fQVJNX0lSUV9WQ1BVMl9NQVNLCQkweGYKICNkZWZpbmUgS1ZN X0FSTV9JUlFfVFlQRV9TSElGVAkJMjQKLSNkZWZpbmUgS1ZNX0FSTV9JUlFfVFlQRV9NQVNLCQkw eGZmCisjZGVmaW5lIEtWTV9BUk1fSVJRX1RZUEVfTUFTSwkJMHhmCiAjZGVmaW5lIEtWTV9BUk1f SVJRX1ZDUFVfU0hJRlQJCTE2CiAjZGVmaW5lIEtWTV9BUk1fSVJRX1ZDUFVfTUFTSwkJMHhmZgog I2RlZmluZSBLVk1fQVJNX0lSUV9OVU1fU0hJRlQJCTAKZGlmZiAtLWdpdCBhL2luY2x1ZGUvdWFw aS9saW51eC9rdm0uaCBiL2luY2x1ZGUvdWFwaS9saW51eC9rdm0uaAppbmRleCA1ZTNmMTJkNTM1 OWUuLjU0MTRiNjU4OGZiYiAxMDA2NDQKLS0tIGEvaW5jbHVkZS91YXBpL2xpbnV4L2t2bS5oCisr KyBiL2luY2x1ZGUvdWFwaS9saW51eC9rdm0uaApAQCAtOTk2LDYgKzk5Niw3IEBAIHN0cnVjdCBr dm1fcHBjX3Jlc2l6ZV9ocHQgewogI2RlZmluZSBLVk1fQ0FQX0FSTV9QVFJBVVRIX0FERFJFU1Mg MTcxCiAjZGVmaW5lIEtWTV9DQVBfQVJNX1BUUkFVVEhfR0VORVJJQyAxNzIKICNkZWZpbmUgS1ZN X0NBUF9QTVVfRVZFTlRfRklMVEVSIDE3MworI2RlZmluZSBLVk1fQ0FQX0FSTV9JUlFfTElORV9M QVlPVVRfMiAxNzQKIAogI2lmZGVmIEtWTV9DQVBfSVJRX1JPVVRJTkcKIApkaWZmIC0tZ2l0IGEv dmlydC9rdm0vYXJtL2FybS5jIGIvdmlydC9rdm0vYXJtL2FybS5jCmluZGV4IDM1YTA2OTgxNWJh Zi4uODZjNmFhMWNiNThlIDEwMDY0NAotLS0gYS92aXJ0L2t2bS9hcm0vYXJtLmMKKysrIGIvdmly dC9rdm0vYXJtL2FybS5jCkBAIC0xOTYsNiArMTk2LDcgQEAgaW50IGt2bV92bV9pb2N0bF9jaGVj a19leHRlbnNpb24oc3RydWN0IGt2bSAqa3ZtLCBsb25nIGV4dCkKIAljYXNlIEtWTV9DQVBfTVBf U1RBVEU6CiAJY2FzZSBLVk1fQ0FQX0lNTUVESUFURV9FWElUOgogCWNhc2UgS1ZNX0NBUF9WQ1BV X0VWRU5UUzoKKwljYXNlIEtWTV9DQVBfQVJNX0lSUV9MSU5FX0xBWU9VVF8yOgogCQlyID0gMTsK IAkJYnJlYWs7CiAJY2FzZSBLVk1fQ0FQX0FSTV9TRVRfREVWSUNFX0FERFI6CkBAIC04ODgsNiAr ODg5LDcgQEAgaW50IGt2bV92bV9pb2N0bF9pcnFfbGluZShzdHJ1Y3Qga3ZtICprdm0sIHN0cnVj dCBrdm1faXJxX2xldmVsICppcnFfbGV2ZWwsCiAKIAlpcnFfdHlwZSA9IChpcnEgPj4gS1ZNX0FS TV9JUlFfVFlQRV9TSElGVCkgJiBLVk1fQVJNX0lSUV9UWVBFX01BU0s7CiAJdmNwdV9pZHggPSAo aXJxID4+IEtWTV9BUk1fSVJRX1ZDUFVfU0hJRlQpICYgS1ZNX0FSTV9JUlFfVkNQVV9NQVNLOwor CXZjcHVfaWR4ICs9ICgoaXJxID4+IEtWTV9BUk1fSVJRX1ZDUFUyX1NISUZUKSAmIEtWTV9BUk1f SVJRX1ZDUFUyX01BU0spICogKEtWTV9BUk1fSVJRX1ZDUFVfTUFTSyArIDEpOwogCWlycV9udW0g PSAoaXJxID4+IEtWTV9BUk1fSVJRX05VTV9TSElGVCkgJiBLVk1fQVJNX0lSUV9OVU1fTUFTSzsK IAogCXRyYWNlX2t2bV9pcnFfbGluZShpcnFfdHlwZSwgdmNwdV9pZHgsIGlycV9udW0sIGlycV9s ZXZlbC0+bGV2ZWwpOwotLSAKMi4yMC4xCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJt LWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21h aWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=