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* [PATCH] drm/i915/tgl: Use refclk/2 as bypass frequency
@ 2019-09-05 18:13 Matt Roper
  2019-09-05 18:54 ` ✓ Fi.CI.BAT: success for " Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 5+ messages in thread
From: Matt Roper @ 2019-09-05 18:13 UTC (permalink / raw)
  To: intel-gfx

Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
TGL runs at refclk/2.  The 50MHz croclk/2 is only used by hardware
during some power state transitions.

Bspec: 49201
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 76f11d465e91..d3e56628af70 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1855,8 +1855,6 @@ static void icl_get_cdclk(struct drm_i915_private *dev_priv,
 	u32 val;
 	int div;
 
-	cdclk_state->bypass = 50000;
-
 	val = I915_READ(SKL_DSSM);
 	switch (val & ICL_DSSM_CDCLK_PLL_REFCLK_MASK) {
 	default:
@@ -1873,6 +1871,11 @@ static void icl_get_cdclk(struct drm_i915_private *dev_priv,
 		break;
 	}
 
+	if (INTEL_GEN(dev_priv) >= 12)
+		cdclk_state->bypass = cdclk_state->ref / 2;
+	else
+		cdclk_state->bypass = 50000;
+
 	val = I915_READ(BXT_DE_PLL_ENABLE);
 	if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
 	    (val & BXT_DE_PLL_LOCK) == 0) {
-- 
2.20.1

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^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2019-09-06 15:45 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2019-09-05 18:13 [PATCH] drm/i915/tgl: Use refclk/2 as bypass frequency Matt Roper
2019-09-05 18:54 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-09-05 23:07 ` ✓ Fi.CI.IGT: " Patchwork
2019-09-06 11:36 ` [PATCH] " Ville Syrjälä
2019-09-06 15:45   ` Matt Roper

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