[PATCH v2] drm/i915: Add TigerLake bandwidth checking

[PATCH v2] drm/i915: Add TigerLake bandwidth checking

[Stanislav Lisovskiy]

Added bandwidth calculation algorithm and checks,
similar way as it was done for ICL, some constants
were corrected according to BSpec.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

v2: Start using same icl_get_bw_info function to avoid
    code duplication. Moved mpagesize to memory info
    related structure as it is now dependant on memory type.
    Fixed qi.t_bl field assignment.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=111600
---
 drivers/gpu/drm/i915/display/intel_bw.c | 31 ++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 688858ebe4d0..c89fcdccac7e 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -19,6 +19,7 @@ struct intel_qgv_info {
 	u8 num_points;
 	u8 num_channels;
 	u8 t_bl;
+	u8 mpagesize;
 	enum intel_dram_type dram_type;
 };
 
@@ -56,7 +57,13 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
 	qi->num_channels = (val & 0xf0) >> 4;
 	qi->num_points = (val & 0xf00) >> 8;
 
-	qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
+	if (IS_GEN(dev_priv, 11)) {
+		qi->mpagesize = 16;
+		qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
+	} else if (IS_GEN(dev_priv, 12)) {
+		qi->mpagesize = qi->dram_type == INTEL_DRAM_DDR4 ? 16 : 32;
+		qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
+	}
 
 	return 0;
 }
@@ -132,20 +139,26 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
 }
 
 struct intel_sa_info {
-	u8 deburst, mpagesize, deprogbwlimit, displayrtids;
+	u16 displayrtids;
+	u8 deburst, deprogbwlimit;
 };
 
 static const struct intel_sa_info icl_sa_info = {
 	.deburst = 8,
-	.mpagesize = 16,
 	.deprogbwlimit = 25, /* GB/s */
 	.displayrtids = 128,
 };
 
-static int icl_get_bw_info(struct drm_i915_private *dev_priv)
+static const struct intel_sa_info tgl_sa_info = {
+	.deburst = 16,
+	.deprogbwlimit = 34, /* GB/s */
+	.displayrtids = 256,
+};
+
+
+static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
 {
 	struct intel_qgv_info qi = {};
-	const struct intel_sa_info *sa = &icl_sa_info;
 	bool is_y_tile = true; /* assume y tile may be used */
 	int num_channels;
 	int deinterleave;
@@ -234,7 +247,9 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
 void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 {
 	if (IS_GEN(dev_priv, 11))
-		icl_get_bw_info(dev_priv);
+		icl_get_bw_info(dev_priv, &icl_sa_info);
+	else if (IS_GEN(dev_priv, 12))
+		icl_get_bw_info(dev_priv, &tgl_sa_info);
 }
 
 static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
@@ -249,6 +264,10 @@ static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
 		return min3(icl_max_bw(dev_priv, num_planes, 0),
 			    icl_max_bw(dev_priv, num_planes, 1),
 			    icl_max_bw(dev_priv, num_planes, 2));
+	else if (IS_GEN(dev_priv, 12))
+		return min3(icl_max_bw(dev_priv, num_planes, 0),
+			    icl_max_bw(dev_priv, num_planes, 1),
+			    icl_max_bw(dev_priv, num_planes, 2));
 	else
 		return UINT_MAX;
 }
-- 
2.17.1

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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Add TigerLake bandwidth checking (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Add TigerLake bandwidth checking (rev2)
URL   : https://patchwork.freedesktop.org/series/66817/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
250507d65db1 drm/i915: Add TigerLake bandwidth checking
-:69: CHECK:LINE_SPACING: Please don't use multiple blank lines
#69: FILE: drivers/gpu/drm/i915/display/intel_bw.c:158:
+
+

total: 0 errors, 0 warnings, 1 checks, 71 lines checked

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✓ Fi.CI.BAT: success for drm/i915: Add TigerLake bandwidth checking (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Add TigerLake bandwidth checking (rev2)
URL   : https://patchwork.freedesktop.org/series/66817/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6913 -> Patchwork_14441
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14441/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14441:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_chamelium@hdmi-hpd-fast:
    - {fi-cml-h}:         NOTRUN -> [SKIP][1] +8 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14441/fi-cml-h/igt@kms_chamelium@hdmi-hpd-fast.html

  
Known issues
------------

  Here are the changes found in Patchwork_14441 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_switch@legacy-render:
    - fi-bxt-dsi:         [PASS][2] -> [INCOMPLETE][3] ([fdo#103927] / [fdo#111381])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6913/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14441/fi-bxt-dsi/igt@gem_ctx_switch@legacy-render.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-ilk-650:         [PASS][4] -> [DMESG-WARN][5] ([fdo#106387]) +1 similar issue
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6913/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14441/fi-ilk-650/igt@prime_vgem@basic-fence-flip.html

  
#### Possible fixes ####

  * igt@gem_render_tiled_blits@basic:
    - {fi-tgl-u}:         [FAIL][6] -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6913/fi-tgl-u/igt@gem_render_tiled_blits@basic.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14441/fi-tgl-u/igt@gem_render_tiled_blits@basic.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][8] ([fdo#111407]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6913/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14441/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#106387]: https://bugs.freedesktop.org/show_bug.cgi?id=106387
  [fdo#111381]: https://bugs.freedesktop.org/show_bug.cgi?id=111381
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600


Participating hosts (55 -> 48)
------------------------------

  Additional (1): fi-cml-h 
  Missing    (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-u3 fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6913 -> Patchwork_14441

  CI-20190529: 20190529
  CI_DRM_6913: 16f20435633153f7d25a061d9fa339fbc0ec123d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5190: 0e9510b83502af3e230870df2d66d4f68918d3a4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14441: 250507d65db179353d74170ffed164ff318a3dae @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

250507d65db1 drm/i915: Add TigerLake bandwidth checking

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14441/index.html
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Re: [PATCH v2] drm/i915: Add TigerLake bandwidth checking

[Ville Syrjälä]

On Wed, Sep 18, 2019 at 12:22:01PM +0300, Stanislav Lisovskiy wrote:
> Added bandwidth calculation algorithm and checks,
> similar way as it was done for ICL, some constants
> were corrected according to BSpec.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> v2: Start using same icl_get_bw_info function to avoid
>     code duplication. Moved mpagesize to memory info
>     related structure as it is now dependant on memory type.
>     Fixed qi.t_bl field assignment.
> 
> Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=111600
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 31 ++++++++++++++++++++-----
>  1 file changed, 25 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 688858ebe4d0..c89fcdccac7e 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -19,6 +19,7 @@ struct intel_qgv_info {
>  	u8 num_points;
>  	u8 num_channels;
>  	u8 t_bl;
> +	u8 mpagesize;

Looks like we're not using this at all. Probably easier to just rip it out
entirely.

>  	enum intel_dram_type dram_type;
>  };
>  
> @@ -56,7 +57,13 @@ static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv,
>  	qi->num_channels = (val & 0xf0) >> 4;
>  	qi->num_points = (val & 0xf00) >> 8;
>  
> -	qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
> +	if (IS_GEN(dev_priv, 11)) {
> +		qi->mpagesize = 16;
> +		qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 8;
> +	} else if (IS_GEN(dev_priv, 12)) {
> +		qi->mpagesize = qi->dram_type == INTEL_DRAM_DDR4 ? 16 : 32;
> +		qi->t_bl = qi->dram_type == INTEL_DRAM_DDR4 ? 4 : 16;
> +	}
>  
>  	return 0;
>  }
> @@ -132,20 +139,26 @@ static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
>  }
>  
>  struct intel_sa_info {
> -	u8 deburst, mpagesize, deprogbwlimit, displayrtids;
> +	u16 displayrtids;
> +	u8 deburst, deprogbwlimit;
>  };
>  
>  static const struct intel_sa_info icl_sa_info = {
>  	.deburst = 8,
> -	.mpagesize = 16,
>  	.deprogbwlimit = 25, /* GB/s */
>  	.displayrtids = 128,
>  };
>  
> -static int icl_get_bw_info(struct drm_i915_private *dev_priv)
> +static const struct intel_sa_info tgl_sa_info = {
> +	.deburst = 16,
> +	.deprogbwlimit = 34, /* GB/s */
> +	.displayrtids = 256,
> +};
> +
> +

Double newline. checkpatch should have complained I think.

> +static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
>  {
>  	struct intel_qgv_info qi = {};
> -	const struct intel_sa_info *sa = &icl_sa_info;
>  	bool is_y_tile = true; /* assume y tile may be used */
>  	int num_channels;
>  	int deinterleave;
> @@ -234,7 +247,9 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
>  void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>  {
>  	if (IS_GEN(dev_priv, 11))
> -		icl_get_bw_info(dev_priv);
> +		icl_get_bw_info(dev_priv, &icl_sa_info);
> +	else if (IS_GEN(dev_priv, 12))
> +		icl_get_bw_info(dev_priv, &tgl_sa_info);

The usual approach is to put the newer platform first.

>  }
>  
>  static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
> @@ -249,6 +264,10 @@ static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
>  		return min3(icl_max_bw(dev_priv, num_planes, 0),
>  			    icl_max_bw(dev_priv, num_planes, 1),
>  			    icl_max_bw(dev_priv, num_planes, 2));
> +	else if (IS_GEN(dev_priv, 12))
> +		return min3(icl_max_bw(dev_priv, num_planes, 0),
> +			    icl_max_bw(dev_priv, num_planes, 1),
> +			    icl_max_bw(dev_priv, num_planes, 2));

Why add another identical branch?

>  	else
>  		return UINT_MAX;
>  }
> -- 
> 2.17.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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