From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [PATCH 00/12] drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output
Date: Fri, 20 Sep 2019 21:48:38 +0300 [thread overview]
Message-ID: <20190920184838.GG1208@intel.com> (raw)
In-Reply-To: <20190718145053.25808-1-ville.syrjala@linux.intel.com>
On Thu, Jul 18, 2019 at 05:50:41PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I was playing around with YCbCr 4:4:4 output and noticed several
> things wrong in our code. So I fixed it all and tossed in the
> prep work for YCbCr 4:4:4 output on ilk+.
>
> Ville Syrjälä (12):
> drm/dp: Add definitons for MSA MISC bits
^ pushed to drm-misc-next
> drm/i915: Switch to using DP_MSA_MISC_* defines
^ on hold until the first patch propagates to dinq.
> drm/i915: Fix HSW+ DP MSA YCbCr colorspace indication
> drm/i915: Fix AVI infoframe quantization range for YCbCr output
> drm/i915: Extract intel_hdmi_limited_color_range()
> drm/i915: Never set limited_color_range=true for YCbCr output
> drm/i915: Don't look at unrelated PIPECONF bits for interlaced readout
> drm/i915: Simplify intel_get_crtc_ycbcr_config()
> drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW
> drm/i915: Document ILK+ pipe csc matrix better
> drm/i915: Set up ILK/SNB csc unit properly for YCbCr output
> drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB
The rest pushed to dinq, with typos fixed. Thanks for the review.
>
> drivers/gpu/drm/i915/display/intel_color.c | 51 ++++++--
> drivers/gpu/drm/i915/display/intel_ddi.c | 28 +++--
> drivers/gpu/drm/i915/display/intel_display.c | 120 ++++++++++++-------
> drivers/gpu/drm/i915/display/intel_dp.c | 10 ++
> drivers/gpu/drm/i915/display/intel_hdmi.c | 61 +++++++---
> drivers/gpu/drm/i915/i915_reg.h | 31 ++---
> include/drm/drm_dp_helper.h | 42 +++++++
> 7 files changed, 247 insertions(+), 96 deletions(-)
>
> --
> 2.21.0
--
Ville Syrjälä
Intel
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prev parent reply other threads:[~2019-09-20 18:48 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-18 14:50 [PATCH 00/12] drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output Ville Syrjala
2019-07-18 14:50 ` [PATCH 01/12] drm/dp: Add definitons for MSA MISC bits Ville Syrjala
2019-09-18 18:55 ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 02/12] drm/i915: Fix HSW+ DP MSA YCbCr colorspace indication Ville Syrjala
2019-09-18 18:59 ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 03/12] drm/i915: Fix AVI infoframe quantization range for YCbCr output Ville Syrjala
2019-09-20 12:56 ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 04/12] drm/i915: Extract intel_hdmi_limited_color_range() Ville Syrjala
2019-09-18 19:00 ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 05/12] drm/i915: Never set limited_color_range=true for YCbCr output Ville Syrjala
2019-07-18 16:45 ` [PATCH v2 " Ville Syrjala
2019-09-18 19:01 ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 06/12] drm/i915: Switch to using DP_MSA_MISC_* defines Ville Syrjala
2019-09-18 19:01 ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 07/12] drm/i915: Don't look at unrelated PIPECONF bits for interlaced readout Ville Syrjala
2019-09-18 19:02 ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 08/12] drm/i915: Simplify intel_get_crtc_ycbcr_config() Ville Syrjala
2019-09-18 19:02 ` Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 09/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for HSW Ville Syrjala
2019-09-18 19:03 ` Mun, Gwan-gyeong
2019-09-20 12:20 ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 10/12] drm/i915: Document ILK+ pipe csc matrix better Ville Syrjala
2019-09-20 14:24 ` [Intel-gfx] " Mun, Gwan-gyeong
2019-09-20 14:29 ` Ville Syrjälä
2019-07-18 14:50 ` [PATCH 11/12] drm/i915: Set up ILK/SNB csc unit properly for YCbCr output Ville Syrjala
2019-09-20 12:19 ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 14:50 ` [PATCH 12/12] drm/i915: Add PIPECONF YCbCr 4:4:4 programming for ILK-IVB Ville Syrjala
2019-09-18 19:05 ` Mun, Gwan-gyeong
2019-09-20 12:21 ` [Intel-gfx] " Mun, Gwan-gyeong
2019-07-18 15:33 ` ✗ Fi.CI.BAT: failure for drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output Patchwork
2019-07-18 17:21 ` ✓ Fi.CI.BAT: success for drm/i915: YCbCr output fixes and prep work for YCbCr 4:4:4 output (rev2) Patchwork
2019-07-18 20:11 ` ✓ Fi.CI.IGT: " Patchwork
2019-09-20 18:48 ` Ville Syrjälä [this message]
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