Re: [PATCH] intel_iommu: TM field should not be in reserved bits

["Michael S. Tsirkin" <mst@redhat.com>]

On Thu, Sep 26, 2019 at 01:49:22PM +0800, qi1.zhang@intel.com wrote:
> From: "Zhang, Qi" <qi1.zhang@intel.com>
> 
> When dt is supported, TM field should not be Reserved(0).
> 
> Refer to VT-d Spec 9.8
> 
> Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
> Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
> ---
>  hw/i386/intel_iommu.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index f1de8fdb75..2696ceeb9d 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -3567,6 +3567,13 @@ static void vtd_init(IntelIOMMUState *s)
>  
>      if (x86_iommu->dt_supported) {
>          s->ecap |= VTD_ECAP_DT;
> +        vtd_paging_entry_rsvd_field[1] &= ~(1ULL << 62);
> +        vtd_paging_entry_rsvd_field[2] &= ~(1ULL << 62);
> +        vtd_paging_entry_rsvd_field[3] &= ~(1ULL << 62);
> +
> +        vtd_paging_entry_rsvd_field[5] &= ~(1ULL << 62);
> +        vtd_paging_entry_rsvd_field[6] &= ~(1ULL << 62);
> +        vtd_paging_entry_rsvd_field[7] &= ~(1ULL << 62);

Add a macro for this value, please.


And I think it's cleaner to pass dt_supported flag
to VTD_SPTE_PAGE_LX_RSVD_MASK and VTD_SPTE_LPAGE_LX_RSVD_MASK,
rather than set bits then clear them selectively.

>      }
>  
>      if (x86_iommu->pt_supported) {
> -- 
> 2.20.1