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[79.176.40.226]) by smtp.gmail.com with ESMTPSA id 54sm2520627qts.75.2019.09.27.02.33.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Sep 2019 02:33:50 -0700 (PDT) Date: Fri, 27 Sep 2019 05:33:45 -0400 From: "Michael S. Tsirkin" To: qi1.zhang@intel.com Subject: Re: [PATCH V2] intel_iommu: TM field should not be in reserved bits Message-ID: <20190927053226-mutt-send-email-mst@kernel.org> References: <20190927045838.2968-1-qi1.zhang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190927045838.2968-1-qi1.zhang@intel.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pbonzini@redhat.com, ehabkost@redhat.com, qemu-devel@nongnu.org, rth@twiddle.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, Sep 27, 2019 at 12:58:38PM +0800, qi1.zhang@intel.com wrote: > From: "Zhang, Qi" > > When dt is supported, TM field should not be Reserved(0). > > Refer to VT-d Spec 9.8 > > Signed-off-by: Zhang, Qi > Signed-off-by: Qi, Yadong > --- > hw/i386/intel_iommu.c | 12 ++++++------ > hw/i386/intel_iommu_internal.h | 25 +++++++++++++++++++------ > 2 files changed, 25 insertions(+), 12 deletions(-) > --- > Changelog V2: > move dt_supported flag to VTD_SPTE_PAGE_LX_RSVD_MASK and VTD_SPTE_LPAGE_LX_RSVD_MASK > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index f1de8fdb75..35222cf55c 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -3548,13 +3548,13 @@ static void vtd_init(IntelIOMMUState *s) > * Rsvd field masks for spte > */ > vtd_paging_entry_rsvd_field[0] = ~0ULL; > - vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits); > - vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits); > - vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits); > + vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits, x86_iommu->dt_supported); > + vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits, x86_iommu->dt_supported); > + vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits, x86_iommu->dt_supported); > vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits); > - vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits); > - vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits); > - vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits); > + vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits, x86_iommu->dt_supported); > + vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, x86_iommu->dt_supported); > + vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, x86_iommu->dt_supported); > vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits); > > if (x86_iommu_ir_supported(x86_iommu)) { > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index c1235a7063..01f1aa6c86 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -387,19 +387,31 @@ typedef union VTDInvDesc VTDInvDesc; > #define VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO 0xffff0000ffe0fff8 > > /* Rsvd field masks for spte */ > -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \ > +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \ > + dt_supported? \ space before ? please. > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) cleaner: 0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | (dt_supported ? VTD_SL_TM : 0x0)) > -#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \ > +#define VTD_SPTE_PAGE_L2_RSVD_MASK(aw, dt_supported) \ > + dt_supported? \ > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > -#define VTD_SPTE_PAGE_L3_RSVD_MASK(aw) \ > +#define VTD_SPTE_PAGE_L3_RSVD_MASK(aw, dt_supported) \ > + dt_supported? \ > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \ > (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > -#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw) \ > +#define VTD_SPTE_LPAGE_L1_RSVD_MASK(aw, dt_supported) \ > + dt_supported? \ > + (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \ > +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \ > + dt_supported? \ > + (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \ > +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \ > + dt_supported? \ > + (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \ > (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > #define VTD_SPTE_LPAGE_L4_RSVD_MASK(aw) \ > (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM)) > @@ -506,5 +518,6 @@ typedef struct VTDRootEntry VTDRootEntry; > #define VTD_SL_W (1ULL << 1) > #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw)) > #define VTD_SL_IGN_COM 0xbff0000000000000ULL > +#define VTD_SL_TM (1ULL << 62) > > #endif > -- > 2.20.1