Re: [PATCH V2] intel_iommu: TM field should not be in reserved bits

[Peter Xu <peterx@redhat.com>]

On Sun, Sep 29, 2019 at 01:11:12AM +0000, Zhang, Qi1 wrote:
> 
> 
> > -----Original Message-----
> > From: Peter Xu <peterx@redhat.com>
> > Sent: Friday, September 27, 2019 5:32 PM
> > To: Zhang, Qi1 <qi1.zhang@intel.com>
> > Cc: qemu-devel@nongnu.org; ehabkost@redhat.com; mst@redhat.com;
> > pbonzini@redhat.com; rth@twiddle.net; Qi, Yadong <yadong.qi@intel.com>
> > Subject: Re: [PATCH V2] intel_iommu: TM field should not be in reserved bits
> > 
> > On Fri, Sep 27, 2019 at 08:03:21AM +0000, Zhang, Qi1 wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Peter Xu <peterx@redhat.com>
> > > > Sent: Friday, September 27, 2019 2:10 PM
> > > > To: Zhang, Qi1 <qi1.zhang@intel.com>
> > > > Cc: qemu-devel@nongnu.org; ehabkost@redhat.com; mst@redhat.com;
> > > > pbonzini@redhat.com; rth@twiddle.net
> > > > Subject: Re: [PATCH V2] intel_iommu: TM field should not be in
> > > > reserved bits
> > > >
> > > > On Fri, Sep 27, 2019 at 12:58:38PM +0800, qi1.zhang@intel.com wrote:
> > > > > From: "Zhang, Qi" <qi1.zhang@intel.com>
> > > > >
> > > > > When dt is supported, TM field should not be Reserved(0).
> > > > >
> > > > > Refer to VT-d Spec 9.8
> > > > >
> > > > > Signed-off-by: Zhang, Qi <qi1.zhang@intel.com>
> > > > > Signed-off-by: Qi, Yadong <yadong.qi@intel.com>
> > > > > ---
> > > > >  hw/i386/intel_iommu.c          | 12 ++++++------
> > > > >  hw/i386/intel_iommu_internal.h | 25 +++++++++++++++++++------
> > > > >  2 files changed, 25 insertions(+), 12 deletions(-)
> > > > > ---
> > VTD_SPTE_PAGE_L2_RSVD_MASK(s-
> > > > >aw_bits);
> > > > > -    vtd_paging_entry_rsvd_field[3] =
> > > > >aw_bits);
> > > > > +    vtd_paging_entry_rsvd_field[5] =
> > > > VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits, x86_iommu-
> > > > >dt_supported);
> > > > > +    vtd_paging_entry_rsvd_field[6] =
> > > > VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits, x86_iommu-
> > > > >dt_supported);
> > > > > +    vtd_paging_entry_rsvd_field[7] =
> > > > > + VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits, x86_iommu-
> > > > >dt_supported);
> > > > >      vtd_paging_entry_rsvd_field[8] =
> > > > >VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
> > > >
> > > > Should this TM bit only affects leaves?  Say, entry 1 (4K), 5 (2M), 6 (1G).

[1]

> > > > While this reminded me that I'm totally confused on why we have had
> > > > entry 7, 8 after all...  Are they really used?
> > > Yes. TM bit only affects. To this array, index 1, 5,6,7 may be leaf. Will update
> > a new patchset for it.
> > 
> > Could I ask why index 7 may be leaf?
> Index 7 is PDPE 1G GB leaf.

I thought 1G was index 6.  I've listed my understanding above [1].
Would you please double confirm?  Thanks,

-- 
Peter Xu