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From: Igor Mammedov <imammedo@redhat.com>
To: Tao Xu <tao3.xu@intel.com>
Cc: ehabkost@redhat.com, jingqi.liu@intel.com, fan.du@intel.com,
	qemu-devel@nongnu.org, Daniel Black <daniel@linux.ibm.com>,
	Jonathan Cameron <Jonathan.Cameron@huawei.com>,
	dan.j.williams@intel.com
Subject: Re: [PATCH v12 10/11] hmat acpi: Build Memory Side Cache Information Structure(s)
Date: Fri, 4 Oct 2019 10:01:57 +0200	[thread overview]
Message-ID: <20191004100157.7e3ce374@redhat.com> (raw)
In-Reply-To: <20190920074349.2616-11-tao3.xu@intel.com>

On Fri, 20 Sep 2019 15:43:48 +0800
Tao Xu <tao3.xu@intel.com> wrote:

> From: Liu Jingqi <jingqi.liu@intel.com>
> 
> This structure describes memory side cache information for memory
> proximity domains if the memory side cache is present and the
> physical device forms the memory side cache.
> The software could use this information to effectively place
> the data in memory to maximize the performance of the system
> memory that use the memory side cache.
> 
> Reviewed-by: Daniel Black <daniel@linux.ibm.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
> Signed-off-by: Tao Xu <tao3.xu@intel.com>
> ---
> 
> No changes in v12.
> 
> Changes in v11:
>     - Move numa option patches forward.
> ---
>  hw/acpi/hmat.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 63 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/acpi/hmat.c b/hw/acpi/hmat.c
> index e7be849581..6b260eeef5 100644
> --- a/hw/acpi/hmat.c
> +++ b/hw/acpi/hmat.c
> @@ -160,13 +160,62 @@ static void build_hmat_lb(GArray *table_data, HMAT_LB_Info *hmat_lb,
>      }
>  }
>  
> +/* ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure: Table 5-147 */
> +static void build_hmat_cache(GArray *table_data, HMAT_Cache_Info *hmat_cache)
> +{
> +    /*
> +     * Cache Attributes: Bits [3:0] – Total Cache Levels
> +     * for this Memory Proximity Domain
> +     */
> +    uint32_t cache_attr = hmat_cache->total_levels & 0xF;
> +
> +    /* Bits [7:4] : Cache Level described in this structure */
> +    cache_attr |= (hmat_cache->level & 0xF) << 4;


> +    /* Bits [11:8] - Cache Associativity */
> +    cache_attr |= (hmat_cache->associativity & 0xF) << 8;
> +
> +    /* Bits [15:12] - Write Policy */
> +    cache_attr |= (hmat_cache->write_policy & 0xF) << 12;

s/0xF/0x7/ for  Cache Associativity /  Write Policy

> +
> +    /* Bits [31:16] - Cache Line size in bytes */
> +    cache_attr |= (hmat_cache->line_size & 0xFFFF) << 16;
> +
> +    cache_attr = cpu_to_le32(cache_attr);
> +
> +    /* Type */
> +    build_append_int_noprefix(table_data, 2, 2);
> +    /* Reserved */
> +    build_append_int_noprefix(table_data, 0, 2);
> +    /* Length */
> +    build_append_int_noprefix(table_data, 32, 4);
> +    /* Proximity Domain for the Memory */
> +    build_append_int_noprefix(table_data, hmat_cache->mem_proximity, 4);
> +    /* Reserved */
> +    build_append_int_noprefix(table_data, 0, 4);
> +    /* Memory Side Cache Size */
> +    build_append_int_noprefix(table_data, hmat_cache->size, 8);
> +    /* Cache Attributes */
> +    build_append_int_noprefix(table_data, cache_attr, 4);
> +    /* Reserved */
> +    build_append_int_noprefix(table_data, 0, 2);
> +    /*
> +     * Number of SMBIOS handles (n)
> +     * Linux kernel uses Memory Side Cache Information Structure
> +     * without SMBIOS entries for now, so set Number of SMBIOS handles
> +     * as 0.
> +     */
> +    build_append_int_noprefix(table_data, 0, 2);
> +}
> +
>  /* Build HMAT sub table structures */
>  static void hmat_build_table_structs(GArray *table_data, NumaState *nstat)
>  {
>      uint16_t flags;
>      uint32_t *initiator_list = NULL;
> -    int i, j, hrchy, type;
> +    int i, j, hrchy, type, level;

s/level/cache_level/

>      HMAT_LB_Info *numa_hmat_lb;
> +    HMAT_Cache_Info *numa_hmat_cache;
>  
>      for (i = 0; i < nstat->num_nodes; i++) {
>          flags = 0;
> @@ -205,6 +254,19 @@ static void hmat_build_table_structs(GArray *table_data, NumaState *nstat)
>          }
>      }
>  
> +    /*
> +     * ACPI 6.3: 5.2.27.5 Memory Side Cache Information Structure:
> +     * Table 5-147
> +     */
> +    for (i = 0; i < nstat->num_nodes; i++) {
> +        for (level = 0; level <= MAX_HMAT_CACHE_LEVEL; level++) {
> +            numa_hmat_cache = nstat->hmat_cache[i][level];
> +            if (numa_hmat_cache) {
> +                build_hmat_cache(table_data, numa_hmat_cache);
> +            }
> +        }
> +    }
> +
>      g_free(initiator_list);
>  }
>  



  reply	other threads:[~2019-10-04  8:03 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-20  7:43 [PATCH v12 00/11] Build ACPI Heterogeneous Memory Attribute Table (HMAT) Tao Xu
2019-09-20  7:43 ` [PATCH v12 01/11] util/cutils: Add qemu_strtotime_ps() Tao Xu
2019-09-20  7:43 ` [PATCH v12 02/11] tests/cutils: Add test for qemu_strtotime_ps() Tao Xu
2019-09-20  7:43 ` [PATCH v12 03/11] qapi: Add builtin type time Tao Xu
2019-10-15  6:22   ` Tao Xu
2019-09-20  7:43 ` [PATCH v12 04/11] tests: Add test for QAPI " Tao Xu
2019-09-20  7:43 ` [PATCH v12 05/11] numa: Extend CLI to provide initiator information for numa nodes Tao Xu
2019-09-30 11:25   ` Igor Mammedov
2019-09-20  7:43 ` [PATCH v12 06/11] numa: Extend CLI to provide memory latency and bandwidth information Tao Xu
2019-10-02 15:16   ` Igor Mammedov
2019-10-09  6:39     ` Tao Xu
2019-10-11 13:56       ` Igor Mammedov
2019-10-12  2:54         ` Tao Xu
2019-09-20  7:43 ` [PATCH v12 07/11] numa: Extend CLI to provide memory side cache information Tao Xu
2019-10-03 11:19   ` Igor Mammedov
2019-10-09  7:54     ` Tao Xu
2019-10-11 14:10       ` Igor Mammedov
2019-09-20  7:43 ` [PATCH v12 08/11] hmat acpi: Build Memory Proximity Domain Attributes Structure(s) Tao Xu
2019-10-03 13:44   ` Igor Mammedov
2019-09-20  7:43 ` [PATCH v12 09/11] hmat acpi: Build System Locality Latency and Bandwidth Information Structure(s) Tao Xu
2019-10-03 14:41   ` Igor Mammedov
2019-10-10  6:53     ` Tao Xu
2019-10-11 14:08       ` Igor Mammedov
2019-10-12  3:04         ` Tao Xu
2019-10-14  9:00           ` Igor Mammedov
2019-10-15  0:59             ` Tao Xu
2019-10-15  5:40               ` Tao Xu
2019-10-17 14:17                 ` Igor Mammedov
2019-09-20  7:43 ` [PATCH v12 10/11] hmat acpi: Build Memory Side Cache " Tao Xu
2019-10-04  8:01   ` Igor Mammedov [this message]
2019-09-20  7:43 ` [PATCH v12 11/11] tests/bios-tables-test: add test cases for ACPI HMAT Tao Xu
2019-10-04  8:08   ` Igor Mammedov
2019-09-21  1:39 ` [PATCH v12 00/11] Build ACPI Heterogeneous Memory Attribute Table (HMAT) no-reply
2019-09-21  1:53 ` no-reply

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