From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A26C9C35280 for ; Tue, 8 Oct 2019 16:02:04 +0000 (UTC) Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by mail.kernel.org (Postfix) with ESMTP id 62F202070B for ; Tue, 8 Oct 2019 16:02:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 62F202070B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=kvmarm-bounces@lists.cs.columbia.edu Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 16F554A8BE; Tue, 8 Oct 2019 12:02:04 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aFfMImLQbjfq; Tue, 8 Oct 2019 12:02:03 -0400 (EDT) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 04D0F4A8D5; Tue, 8 Oct 2019 12:02:02 -0400 (EDT) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 9F5A94A852 for ; Tue, 8 Oct 2019 12:02:00 -0400 (EDT) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id admNhWvlAzAS for ; Tue, 8 Oct 2019 12:01:55 -0400 (EDT) Received: from inca-roads.misterjones.org (inca-roads.misterjones.org [213.251.177.50]) by mm01.cs.columbia.edu (Postfix) with ESMTPS id AD52E4A84A for ; Tue, 8 Oct 2019 12:01:55 -0400 (EDT) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.lan) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:DHE-RSA-AES128-GCM-SHA256:128) (Exim 4.80) (envelope-from ) id 1iHrvu-0001rs-MD; Tue, 08 Oct 2019 18:01:54 +0200 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: [PATCH v2 4/5] arm64: perf: Add reload-on-overflow capability Date: Tue, 8 Oct 2019 17:01:27 +0100 Message-Id: <20191008160128.8872-5-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008160128.8872-1-maz@kernel.org> References: <20191008160128.8872-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, will@kernel.org, mark.rutland@arm.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, andrew.murray@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false Cc: Will Deacon X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu As KVM uses perf as a way to emulate an ARMv8 PMU, it needs to be able to change the sample period as part of the overflow handling (once an overflow has taken place, the following overflow point is the overflow of the virtual counter). Deleting and recreating the in-kernel event is difficult, as we're in interrupt context. Instead, we can teach the PMU driver a new trick, which is to stop the event before the overflow handling, and reprogram it once it has been handled. This would give KVM the opportunity to adjust the next sample period. This feature is gated on a new flag that can get set by KVM in a subsequent patch. Whilst we're at it, move the CHAINED flag from the KVM emulation to the perf_event.h file and adjust the PMU code accordingly. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/perf_event.h | 4 ++++ arch/arm64/kernel/perf_event.c | 8 +++++++- virt/kvm/arm/pmu.c | 4 +--- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h index 2bdbc79bbd01..8b6b38f2db8e 100644 --- a/arch/arm64/include/asm/perf_event.h +++ b/arch/arm64/include/asm/perf_event.h @@ -223,4 +223,8 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs); (regs)->pstate = PSR_MODE_EL1h; \ } +/* Flags used by KVM, among others */ +#define PERF_ATTR_CFG1_CHAINED_EVENT (1U << 0) +#define PERF_ATTR_CFG1_RELOAD_EVENT (1U << 1) + #endif diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index a0b4f1bca491..98907c9e5508 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -322,7 +322,7 @@ PMU_FORMAT_ATTR(long, "config1:0"); static inline bool armv8pmu_event_is_64bit(struct perf_event *event) { - return event->attr.config1 & 0x1; + return event->attr.config1 & PERF_ATTR_CFG1_CHAINED_EVENT; } static struct attribute *armv8_pmuv3_format_attrs[] = { @@ -736,8 +736,14 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) if (!armpmu_event_set_period(event)) continue; + if (event->attr.config1 & PERF_ATTR_CFG1_RELOAD_EVENT) + cpu_pmu->pmu.stop(event, PERF_EF_RELOAD); + if (perf_event_overflow(event, &data, regs)) cpu_pmu->disable(event); + + if (event->attr.config1 & PERF_ATTR_CFG1_RELOAD_EVENT) + cpu_pmu->pmu.start(event, PERF_EF_RELOAD); } armv8pmu_start(cpu_pmu); diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index f291d4ac3519..25a483a04beb 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -15,8 +15,6 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx); -#define PERF_ATTR_CFG1_KVM_PMU_CHAINED 0x1 - /** * kvm_pmu_idx_is_64bit - determine if select_idx is a 64bit counter * @vcpu: The vcpu pointer @@ -570,7 +568,7 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) */ attr.sample_period = (-counter) & GENMASK(63, 0); if (kvm_pmu_counter_is_enabled(vcpu, pmc->idx + 1)) - attr.config1 |= PERF_ATTR_CFG1_KVM_PMU_CHAINED; + attr.config1 |= PERF_ATTR_CFG1_CHAINED_EVENT; event = perf_event_create_kernel_counter(&attr, -1, current, kvm_pmu_perf_overflow, -- 2.20.1 _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95FB5C4360C for ; Tue, 8 Oct 2019 16:02:01 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6CA662070B for ; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.2 #3 (Red Hat Linux)) id 1iHrw0-00029p-P7; Tue, 08 Oct 2019 16:02:00 +0000 Received: from inca-roads.misterjones.org ([213.251.177.50]) by bombadil.infradead.org with esmtps (Exim 4.92.2 #3 (Red Hat Linux)) id 1iHrvw-00027c-VA for linux-arm-kernel@lists.infradead.org; Tue, 08 Oct 2019 16:01:58 +0000 Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=why.lan) by cheepnis.misterjones.org with esmtpsa (TLSv1.2:DHE-RSA-AES128-GCM-SHA256:128) (Exim 4.80) (envelope-from ) id 1iHrvu-0001rs-MD; Tue, 08 Oct 2019 18:01:54 +0200 From: Marc Zyngier To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org Subject: [PATCH v2 4/5] arm64: perf: Add reload-on-overflow capability Date: Tue, 8 Oct 2019 17:01:27 +0100 Message-Id: <20191008160128.8872-5-maz@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191008160128.8872-1-maz@kernel.org> References: <20191008160128.8872-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, will@kernel.org, mark.rutland@arm.com, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, andrew.murray@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191008_090157_165560_E48B221F X-CRM114-Status: GOOD ( 14.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Suzuki K Poulose , James Morse , Andrew Murray , Will Deacon , Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org As KVM uses perf as a way to emulate an ARMv8 PMU, it needs to be able to change the sample period as part of the overflow handling (once an overflow has taken place, the following overflow point is the overflow of the virtual counter). Deleting and recreating the in-kernel event is difficult, as we're in interrupt context. Instead, we can teach the PMU driver a new trick, which is to stop the event before the overflow handling, and reprogram it once it has been handled. This would give KVM the opportunity to adjust the next sample period. This feature is gated on a new flag that can get set by KVM in a subsequent patch. Whilst we're at it, move the CHAINED flag from the KVM emulation to the perf_event.h file and adjust the PMU code accordingly. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/perf_event.h | 4 ++++ arch/arm64/kernel/perf_event.c | 8 +++++++- virt/kvm/arm/pmu.c | 4 +--- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h index 2bdbc79bbd01..8b6b38f2db8e 100644 --- a/arch/arm64/include/asm/perf_event.h +++ b/arch/arm64/include/asm/perf_event.h @@ -223,4 +223,8 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs); (regs)->pstate = PSR_MODE_EL1h; \ } +/* Flags used by KVM, among others */ +#define PERF_ATTR_CFG1_CHAINED_EVENT (1U << 0) +#define PERF_ATTR_CFG1_RELOAD_EVENT (1U << 1) + #endif diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index a0b4f1bca491..98907c9e5508 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -322,7 +322,7 @@ PMU_FORMAT_ATTR(long, "config1:0"); static inline bool armv8pmu_event_is_64bit(struct perf_event *event) { - return event->attr.config1 & 0x1; + return event->attr.config1 & PERF_ATTR_CFG1_CHAINED_EVENT; } static struct attribute *armv8_pmuv3_format_attrs[] = { @@ -736,8 +736,14 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) if (!armpmu_event_set_period(event)) continue; + if (event->attr.config1 & PERF_ATTR_CFG1_RELOAD_EVENT) + cpu_pmu->pmu.stop(event, PERF_EF_RELOAD); + if (perf_event_overflow(event, &data, regs)) cpu_pmu->disable(event); + + if (event->attr.config1 & PERF_ATTR_CFG1_RELOAD_EVENT) + cpu_pmu->pmu.start(event, PERF_EF_RELOAD); } armv8pmu_start(cpu_pmu); diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index f291d4ac3519..25a483a04beb 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -15,8 +15,6 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx); -#define PERF_ATTR_CFG1_KVM_PMU_CHAINED 0x1 - /** * kvm_pmu_idx_is_64bit - determine if select_idx is a 64bit counter * @vcpu: The vcpu pointer @@ -570,7 +568,7 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) */ attr.sample_period = (-counter) & GENMASK(63, 0); if (kvm_pmu_counter_is_enabled(vcpu, pmc->idx + 1)) - attr.config1 |= PERF_ATTR_CFG1_KVM_PMU_CHAINED; + attr.config1 |= PERF_ATTR_CFG1_CHAINED_EVENT; event = perf_event_create_kernel_counter(&attr, -1, current, kvm_pmu_perf_overflow, -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12E8EC35280 for ; Tue, 8 Oct 2019 16:01:58 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DF9392070B for ; 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SAEximRunCond expanded to false Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org As KVM uses perf as a way to emulate an ARMv8 PMU, it needs to be able to change the sample period as part of the overflow handling (once an overflow has taken place, the following overflow point is the overflow of the virtual counter). Deleting and recreating the in-kernel event is difficult, as we're in interrupt context. Instead, we can teach the PMU driver a new trick, which is to stop the event before the overflow handling, and reprogram it once it has been handled. This would give KVM the opportunity to adjust the next sample period. This feature is gated on a new flag that can get set by KVM in a subsequent patch. Whilst we're at it, move the CHAINED flag from the KVM emulation to the perf_event.h file and adjust the PMU code accordingly. Signed-off-by: Marc Zyngier --- arch/arm64/include/asm/perf_event.h | 4 ++++ arch/arm64/kernel/perf_event.c | 8 +++++++- virt/kvm/arm/pmu.c | 4 +--- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/perf_event.h b/arch/arm64/include/asm/perf_event.h index 2bdbc79bbd01..8b6b38f2db8e 100644 --- a/arch/arm64/include/asm/perf_event.h +++ b/arch/arm64/include/asm/perf_event.h @@ -223,4 +223,8 @@ extern unsigned long perf_misc_flags(struct pt_regs *regs); (regs)->pstate = PSR_MODE_EL1h; \ } +/* Flags used by KVM, among others */ +#define PERF_ATTR_CFG1_CHAINED_EVENT (1U << 0) +#define PERF_ATTR_CFG1_RELOAD_EVENT (1U << 1) + #endif diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index a0b4f1bca491..98907c9e5508 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -322,7 +322,7 @@ PMU_FORMAT_ATTR(long, "config1:0"); static inline bool armv8pmu_event_is_64bit(struct perf_event *event) { - return event->attr.config1 & 0x1; + return event->attr.config1 & PERF_ATTR_CFG1_CHAINED_EVENT; } static struct attribute *armv8_pmuv3_format_attrs[] = { @@ -736,8 +736,14 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) if (!armpmu_event_set_period(event)) continue; + if (event->attr.config1 & PERF_ATTR_CFG1_RELOAD_EVENT) + cpu_pmu->pmu.stop(event, PERF_EF_RELOAD); + if (perf_event_overflow(event, &data, regs)) cpu_pmu->disable(event); + + if (event->attr.config1 & PERF_ATTR_CFG1_RELOAD_EVENT) + cpu_pmu->pmu.start(event, PERF_EF_RELOAD); } armv8pmu_start(cpu_pmu); diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c index f291d4ac3519..25a483a04beb 100644 --- a/virt/kvm/arm/pmu.c +++ b/virt/kvm/arm/pmu.c @@ -15,8 +15,6 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx); -#define PERF_ATTR_CFG1_KVM_PMU_CHAINED 0x1 - /** * kvm_pmu_idx_is_64bit - determine if select_idx is a 64bit counter * @vcpu: The vcpu pointer @@ -570,7 +568,7 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx) */ attr.sample_period = (-counter) & GENMASK(63, 0); if (kvm_pmu_counter_is_enabled(vcpu, pmc->idx + 1)) - attr.config1 |= PERF_ATTR_CFG1_KVM_PMU_CHAINED; + attr.config1 |= PERF_ATTR_CFG1_CHAINED_EVENT; event = perf_event_create_kernel_counter(&attr, -1, current, kvm_pmu_perf_overflow, -- 2.20.1