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Thu, 10 Oct 2019 13:26:02 +0000 From: Ayan Halder To: Neil Armstrong Subject: Re: [PATCH 4/7] drm/meson: plane: add support for AFBC mode for OSD1 plane Thread-Topic: [PATCH 4/7] drm/meson: plane: add support for AFBC mode for OSD1 plane Thread-Index: AQHVf0yriLjFzO5S+ESDJ/ifpM4kuqdT3eqA Date: Thu, 10 Oct 2019 13:26:02 +0000 Message-ID: <20191010132601.GA10110@arm.com> References: <20191010092526.10419-1-narmstrong@baylibre.com> <20191010092526.10419-5-narmstrong@baylibre.com> In-Reply-To: <20191010092526.10419-5-narmstrong@baylibre.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LNXP265CA0009.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:5e::21) To AM0PR08MB5345.eurprd08.prod.outlook.com (2603:10a6:208:18c::21) Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Ayan.Halder@arm.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [217.140.106.53] x-ms-publictraffictype: Email X-MS-Office365-Filtering-Correlation-Id: b6e9bca8-a7a1-4164-cfa1-08d74d856b0f X-MS-Office365-Filtering-HT: Tenant X-MS-TrafficTypeDiagnostic: AM0PR08MB4098:|VI1PR08MB4288: X-MS-Exchange-PUrlCount: 1 X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:317;OLM:317; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB4288 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191010_062620_670259_5B75BF57 X-CRM114-Status: GOOD ( 19.07 ) X-BeenThere: linux-amlogic@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "khilman@baylibre.com" , nd , "linux-arm-kernel@lists.infradead.org" , "dri-devel@lists.freedesktop.org" , "linux-amlogic@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-amlogic" Errors-To: linux-amlogic-bounces+linux-amlogic=archiver.kernel.org@lists.infradead.org On Thu, Oct 10, 2019 at 11:25:23AM +0200, Neil Armstrong wrote: > This adds all the OSD configuration plumbing to support the AFBC decoders > path to display of the OSD1 plane. > > The Amlogic GXM and G12A AFBC decoders are integrated very differently. > > The Amlogic GXM has a direct output path to the OSD1 VIU pixel input, > because the GXM AFBC decoder seem to be a custom IP developed by Amlogic. > > On the other side, the Amlogic G12A AFBC decoder seems to be an external > IP that emit pixels on an AXI master hooked to a "Mali Unpack" block > feeding the OSD1 VIU pixel input. > This uses a weird "0x1000000" internal HW physical address on both > sides to transfer the pixels. > > For Amlogic GXM, the supported pixel formats are the same as the normal > linear OSD1 mode. > > On the other side, Amlogic added support for all AFBC v1.2 formats for > the G12A AFBC integration. > > For simplicity, we stick to the already supported formats for now. > > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/meson/meson_crtc.c | 2 + > drivers/gpu/drm/meson/meson_drv.h | 4 + > drivers/gpu/drm/meson/meson_plane.c | 215 ++++++++++++++++++++++++---- > 3 files changed, 190 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c > index 57ae1c13d1e6..d478fa232951 100644 > --- a/drivers/gpu/drm/meson/meson_crtc.c > +++ b/drivers/gpu/drm/meson/meson_crtc.c > @@ -281,6 +281,8 @@ void meson_crtc_irq(struct meson_drm *priv) > if (priv->viu.osd1_enabled && priv->viu.osd1_commit) { > writel_relaxed(priv->viu.osd1_ctrl_stat, > priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); > + writel_relaxed(priv->viu.osd1_ctrl_stat2, > + priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > writel_relaxed(priv->viu.osd1_blk0_cfg[0], > priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); > writel_relaxed(priv->viu.osd1_blk0_cfg[1], > diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h > index 60f13c6f34e5..de25349be8aa 100644 > --- a/drivers/gpu/drm/meson/meson_drv.h > +++ b/drivers/gpu/drm/meson/meson_drv.h > @@ -53,8 +53,12 @@ struct meson_drm { > bool osd1_enabled; > bool osd1_interlace; > bool osd1_commit; > + bool osd1_afbcd; > uint32_t osd1_ctrl_stat; > + uint32_t osd1_ctrl_stat2; > uint32_t osd1_blk0_cfg[5]; > + uint32_t osd1_blk1_cfg4; > + uint32_t osd1_blk2_cfg4; > uint32_t osd1_addr; > uint32_t osd1_stride; > uint32_t osd1_height; > diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c > index 5e798c276037..412941aa8402 100644 > --- a/drivers/gpu/drm/meson/meson_plane.c > +++ b/drivers/gpu/drm/meson/meson_plane.c > @@ -23,6 +23,7 @@ > #include "meson_plane.h" > #include "meson_registers.h" > #include "meson_viu.h" > +#include "meson_osd_afbcd.h" > > /* OSD_SCI_WH_M1 */ > #define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w) > @@ -92,12 +93,38 @@ static int meson_plane_atomic_check(struct drm_plane *plane, > false, true); > } > > +#define MESON_MOD_AFBC_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | \ > + AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | \ > + AFBC_FORMAT_MOD_YTR | \ > + AFBC_FORMAT_MOD_SPARSE | \ > + AFBC_FORMAT_MOD_SPLIT) > + > /* Takes a fixed 16.16 number and converts it to integer. */ > static inline int64_t fixed16_to_int(int64_t value) > { > return value >> 16; > } > > +static u32 meson_g12a_afbcd_line_stride(struct meson_drm *priv) > +{ > + u32 line_stride = 0; > + > + switch (priv->afbcd.format) { > + case DRM_FORMAT_RGB565: > + line_stride = ((priv->viu.osd1_width << 4) + 127) >> 7; > + break; > + case DRM_FORMAT_RGB888: > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_ARGB8888: > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: Please have a look at https://www.kernel.org/doc/html/latest/gpu/afbc.html for our recommendation. We suggest that *X* formats are avoided. Also, for interoperability and maximum compression efficiency (with AFBC_FORMAT_MOD_YTR), we suggest the following order :- Component 0: R Component 1: G Component 2: B Component 3: A (if available) Thus, DRM_FORMAT_ABGR, DRM_FORMAT_BGR should only be allowed. > + line_stride = ((priv->viu.osd1_width << 5) + 127) >> 7; > + break; > + } > + > + return ((line_stride + 1) >> 1) << 1; > +} > + > static void meson_plane_atomic_update(struct drm_plane *plane, > struct drm_plane_state *old_state) > { > @@ -126,57 +153,88 @@ static void meson_plane_atomic_update(struct drm_plane *plane, > */ > spin_lock_irqsave(&priv->drm->event_lock, flags); > > + /* Check if AFBC decoder is required for this buffer */ > + if ((meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || > + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) && > + fb->modifier & DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS)) > + priv->viu.osd1_afbcd = true; > + else > + priv->viu.osd1_afbcd = false; > + > /* Enable OSD and BLK0, set max global alpha */ > priv->viu.osd1_ctrl_stat = OSD_ENABLE | > (0xFF << OSD_GLOBAL_ALPHA_SHIFT) | > OSD_BLK0_ENABLE; > > + priv->viu.osd1_ctrl_stat2 = readl(priv->io_base + > + _REG(VIU_OSD1_CTRL_STAT2)); > + > canvas_id_osd1 = priv->canvas_id_osd1; > > /* Set up BLK0 to point to the right canvas */ > - priv->viu.osd1_blk0_cfg[0] = ((canvas_id_osd1 << OSD_CANVAS_SEL) | > - OSD_ENDIANNESS_LE); > + priv->viu.osd1_blk0_cfg[0] = canvas_id_osd1 << OSD_CANVAS_SEL; > + > + if (priv->viu.osd1_afbcd) { > + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { > + /* This is the internal decoding memory address */ > + priv->viu.osd1_blk1_cfg4 = MESON_G12A_AFBCD_OUT_ADDR; > + priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_BE; > + priv->viu.osd1_ctrl_stat2 |= OSD_PENDING_STAT_CLEAN; > + } > + > + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) { > + priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE; > + priv->viu.osd1_ctrl_stat2 |= OSD_DPATH_MALI_AFBCD; > + } > + } else { > + priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE; > + > + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) > + priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD; > + } > > /* On GXBB, Use the old non-HDR RGB2YUV converter */ > if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) > priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; > > + if (priv->viu.osd1_afbcd && > + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { > + priv->viu.osd1_blk0_cfg[0] |= OSD_MALI_SRC_EN | > + priv->afbcd.ops->fmt_to_blk_mode(fb->modifier, > + fb->format->format); > + } else { > + switch (fb->format->format) { > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_ARGB8888: > + priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > + OSD_COLOR_MATRIX_32_ARGB; > + break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > + OSD_COLOR_MATRIX_32_ABGR; > + break; > + case DRM_FORMAT_RGB888: > + priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 | > + OSD_COLOR_MATRIX_24_RGB; > + break; > + case DRM_FORMAT_RGB565: > + priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 | > + OSD_COLOR_MATRIX_16_RGB565; > + break; > + }; > + } > + > switch (fb->format->format) { > case DRM_FORMAT_XRGB8888: > - /* For XRGB, replace the pixel's alpha by 0xFF */ > - writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, > - priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > - OSD_COLOR_MATRIX_32_ARGB; > - break; > case DRM_FORMAT_XBGR8888: > /* For XRGB, replace the pixel's alpha by 0xFF */ > - writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, > - priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > - OSD_COLOR_MATRIX_32_ABGR; > + priv->viu.osd1_ctrl_stat2 |= OSD_REPLACE_EN; > break; > case DRM_FORMAT_ARGB8888: > - /* For ARGB, use the pixel's alpha */ > - writel_bits_relaxed(OSD_REPLACE_EN, 0, > - priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > - OSD_COLOR_MATRIX_32_ARGB; > - break; > case DRM_FORMAT_ABGR8888: > /* For ARGB, use the pixel's alpha */ > - writel_bits_relaxed(OSD_REPLACE_EN, 0, > - priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > - OSD_COLOR_MATRIX_32_ABGR; > - break; > - case DRM_FORMAT_RGB888: > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 | > - OSD_COLOR_MATRIX_24_RGB; > - break; > - case DRM_FORMAT_RGB565: > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 | > - OSD_COLOR_MATRIX_16_RGB565; > + priv->viu.osd1_ctrl_stat2 &= ~OSD_REPLACE_EN; > break; > }; > > @@ -307,6 +365,16 @@ static void meson_plane_atomic_update(struct drm_plane *plane, > priv->viu.osd1_height = fb->height; > priv->viu.osd1_width = fb->width; > > + if (priv->viu.osd1_afbcd) { > + priv->afbcd.modifier = fb->modifier; > + priv->afbcd.format = fb->format->format; > + > + /* Calculate decoder write stride */ > + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) > + priv->viu.osd1_blk2_cfg4 = > + meson_g12a_afbcd_line_stride(priv); > + } > + > if (!meson_plane->enabled) { > /* Reset OSD1 before enabling it on GXL+ SoCs */ > if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || > @@ -346,6 +414,42 @@ static const struct drm_plane_helper_funcs meson_plane_helper_funcs = { > .prepare_fb = drm_gem_fb_prepare_fb, > }; > > +static bool meson_plane_format_mod_supported(struct drm_plane *plane, > + u32 format, u64 modifier) > +{ > + struct meson_plane *meson_plane = to_meson_plane(plane); > + struct meson_drm *priv = meson_plane->priv; > + int i; > + > + if (modifier == DRM_FORMAT_MOD_INVALID) > + return false; > + > + if (modifier == DRM_FORMAT_MOD_LINEAR) > + return true; > + > + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) && > + !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) > + return false; > + > + if (modifier & ~DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS)) > + return false; > + > + for (i = 0 ; i < plane->modifier_count ; ++i) > + if (plane->modifiers[i] == modifier) > + break; > + > + if (i == plane->modifier_count) { > + DRM_DEBUG_KMS("Unsupported modifier\n"); > + return false; > + } > + > + if (priv->afbcd.ops && priv->afbcd.ops->supported_fmt) > + return priv->afbcd.ops->supported_fmt(modifier, format); > + > + DRM_DEBUG_KMS("AFBC Unsupported\n"); > + return false; > +} > + > static const struct drm_plane_funcs meson_plane_funcs = { > .update_plane = drm_atomic_helper_update_plane, > .disable_plane = drm_atomic_helper_disable_plane, > @@ -353,6 +457,7 @@ static const struct drm_plane_funcs meson_plane_funcs = { > .reset = drm_atomic_helper_plane_reset, > .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, > .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, > + .format_mod_supported = meson_plane_format_mod_supported, > }; > > static const uint32_t supported_drm_formats[] = { > @@ -364,10 +469,53 @@ static const uint32_t supported_drm_formats[] = { > DRM_FORMAT_RGB565, > }; > > +static const uint64_t format_modifiers_afbc_gxm[] = { > + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > + AFBC_FORMAT_MOD_SPARSE | > + AFBC_FORMAT_MOD_YTR), > + /* SPLIT mandates SPARSE, RGB modes mandates YTR */ > + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > + AFBC_FORMAT_MOD_YTR | > + AFBC_FORMAT_MOD_SPARSE | > + AFBC_FORMAT_MOD_SPLIT), > + DRM_FORMAT_MOD_LINEAR, > + DRM_FORMAT_MOD_INVALID, > +}; > + > +static const uint64_t format_modifiers_afbc_g12a[] = { > + /* > + * - TOFIX Support AFBC modifiers for YUV formats (16x16 + TILED) > + * - AFBC_FORMAT_MOD_YTR is mandatory since we only support RGB > + * - SPLIT is mandatory for performances reasons when in 16x16 > + * block size > + * - 32x8 block size + SPLIT is mandatory with 4K frame size > + * for performances reasons > + */ > + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > + AFBC_FORMAT_MOD_YTR | > + AFBC_FORMAT_MOD_SPARSE | > + AFBC_FORMAT_MOD_SPLIT), > + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | > + AFBC_FORMAT_MOD_YTR | > + AFBC_FORMAT_MOD_SPARSE), > + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | > + AFBC_FORMAT_MOD_YTR | > + AFBC_FORMAT_MOD_SPARSE | > + AFBC_FORMAT_MOD_SPLIT), > + DRM_FORMAT_MOD_LINEAR, > + DRM_FORMAT_MOD_INVALID, > +}; > + > +static const uint64_t format_modifiers_default[] = { > + DRM_FORMAT_MOD_LINEAR, > + DRM_FORMAT_MOD_INVALID, > +}; > + > int meson_plane_create(struct meson_drm *priv) > { > struct meson_plane *meson_plane; > struct drm_plane *plane; > + const uint64_t *format_modifiers = format_modifiers_default; > > meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), > GFP_KERNEL); > @@ -377,11 +525,16 @@ int meson_plane_create(struct meson_drm *priv) > meson_plane->priv = priv; > plane = &meson_plane->base; > > + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) > + format_modifiers = format_modifiers_afbc_gxm; > + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) > + format_modifiers = format_modifiers_afbc_g12a; > + > drm_universal_plane_init(priv->drm, plane, 0xFF, > &meson_plane_funcs, > supported_drm_formats, > ARRAY_SIZE(supported_drm_formats), > - NULL, > + format_modifiers, > DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); > > drm_plane_helper_add(plane, &meson_plane_helper_funcs); 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Thu, 10 Oct 2019 13:26:02 +0000 From: Ayan Halder To: Neil Armstrong Subject: Re: [PATCH 4/7] drm/meson: plane: add support for AFBC mode for OSD1 plane Thread-Topic: [PATCH 4/7] drm/meson: plane: add support for AFBC mode for OSD1 plane Thread-Index: AQHVf0yriLjFzO5S+ESDJ/ifpM4kuqdT3eqA Date: Thu, 10 Oct 2019 13:26:02 +0000 Message-ID: <20191010132601.GA10110@arm.com> References: <20191010092526.10419-1-narmstrong@baylibre.com> <20191010092526.10419-5-narmstrong@baylibre.com> In-Reply-To: <20191010092526.10419-5-narmstrong@baylibre.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: LNXP265CA0009.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:5e::21) To AM0PR08MB5345.eurprd08.prod.outlook.com (2603:10a6:208:18c::21) Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Ayan.Halder@arm.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [217.140.106.53] x-ms-publictraffictype: Email X-MS-Office365-Filtering-Correlation-Id: b6e9bca8-a7a1-4164-cfa1-08d74d856b0f X-MS-Office365-Filtering-HT: Tenant X-MS-TrafficTypeDiagnostic: AM0PR08MB4098:|VI1PR08MB4288: X-MS-Exchange-PUrlCount: 1 X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:317;OLM:317; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR08MB4288 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191010_062620_670259_5B75BF57 X-CRM114-Status: GOOD ( 19.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "khilman@baylibre.com" , nd , "linux-arm-kernel@lists.infradead.org" , "dri-devel@lists.freedesktop.org" , "linux-amlogic@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 10, 2019 at 11:25:23AM +0200, Neil Armstrong wrote: > This adds all the OSD configuration plumbing to support the AFBC decoders > path to display of the OSD1 plane. > > The Amlogic GXM and G12A AFBC decoders are integrated very differently. > > The Amlogic GXM has a direct output path to the OSD1 VIU pixel input, > because the GXM AFBC decoder seem to be a custom IP developed by Amlogic. > > On the other side, the Amlogic G12A AFBC decoder seems to be an external > IP that emit pixels on an AXI master hooked to a "Mali Unpack" block > feeding the OSD1 VIU pixel input. > This uses a weird "0x1000000" internal HW physical address on both > sides to transfer the pixels. > > For Amlogic GXM, the supported pixel formats are the same as the normal > linear OSD1 mode. > > On the other side, Amlogic added support for all AFBC v1.2 formats for > the G12A AFBC integration. > > For simplicity, we stick to the already supported formats for now. > > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/meson/meson_crtc.c | 2 + > drivers/gpu/drm/meson/meson_drv.h | 4 + > drivers/gpu/drm/meson/meson_plane.c | 215 ++++++++++++++++++++++++---- > 3 files changed, 190 insertions(+), 31 deletions(-) > > diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c > index 57ae1c13d1e6..d478fa232951 100644 > --- a/drivers/gpu/drm/meson/meson_crtc.c > +++ b/drivers/gpu/drm/meson/meson_crtc.c > @@ -281,6 +281,8 @@ void meson_crtc_irq(struct meson_drm *priv) > if (priv->viu.osd1_enabled && priv->viu.osd1_commit) { > writel_relaxed(priv->viu.osd1_ctrl_stat, > priv->io_base + _REG(VIU_OSD1_CTRL_STAT)); > + writel_relaxed(priv->viu.osd1_ctrl_stat2, > + priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > writel_relaxed(priv->viu.osd1_blk0_cfg[0], > priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0)); > writel_relaxed(priv->viu.osd1_blk0_cfg[1], > diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h > index 60f13c6f34e5..de25349be8aa 100644 > --- a/drivers/gpu/drm/meson/meson_drv.h > +++ b/drivers/gpu/drm/meson/meson_drv.h > @@ -53,8 +53,12 @@ struct meson_drm { > bool osd1_enabled; > bool osd1_interlace; > bool osd1_commit; > + bool osd1_afbcd; > uint32_t osd1_ctrl_stat; > + uint32_t osd1_ctrl_stat2; > uint32_t osd1_blk0_cfg[5]; > + uint32_t osd1_blk1_cfg4; > + uint32_t osd1_blk2_cfg4; > uint32_t osd1_addr; > uint32_t osd1_stride; > uint32_t osd1_height; > diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c > index 5e798c276037..412941aa8402 100644 > --- a/drivers/gpu/drm/meson/meson_plane.c > +++ b/drivers/gpu/drm/meson/meson_plane.c > @@ -23,6 +23,7 @@ > #include "meson_plane.h" > #include "meson_registers.h" > #include "meson_viu.h" > +#include "meson_osd_afbcd.h" > > /* OSD_SCI_WH_M1 */ > #define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w) > @@ -92,12 +93,38 @@ static int meson_plane_atomic_check(struct drm_plane *plane, > false, true); > } > > +#define MESON_MOD_AFBC_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | \ > + AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | \ > + AFBC_FORMAT_MOD_YTR | \ > + AFBC_FORMAT_MOD_SPARSE | \ > + AFBC_FORMAT_MOD_SPLIT) > + > /* Takes a fixed 16.16 number and converts it to integer. */ > static inline int64_t fixed16_to_int(int64_t value) > { > return value >> 16; > } > > +static u32 meson_g12a_afbcd_line_stride(struct meson_drm *priv) > +{ > + u32 line_stride = 0; > + > + switch (priv->afbcd.format) { > + case DRM_FORMAT_RGB565: > + line_stride = ((priv->viu.osd1_width << 4) + 127) >> 7; > + break; > + case DRM_FORMAT_RGB888: > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_ARGB8888: > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: Please have a look at https://www.kernel.org/doc/html/latest/gpu/afbc.html for our recommendation. We suggest that *X* formats are avoided. Also, for interoperability and maximum compression efficiency (with AFBC_FORMAT_MOD_YTR), we suggest the following order :- Component 0: R Component 1: G Component 2: B Component 3: A (if available) Thus, DRM_FORMAT_ABGR, DRM_FORMAT_BGR should only be allowed. > + line_stride = ((priv->viu.osd1_width << 5) + 127) >> 7; > + break; > + } > + > + return ((line_stride + 1) >> 1) << 1; > +} > + > static void meson_plane_atomic_update(struct drm_plane *plane, > struct drm_plane_state *old_state) > { > @@ -126,57 +153,88 @@ static void meson_plane_atomic_update(struct drm_plane *plane, > */ > spin_lock_irqsave(&priv->drm->event_lock, flags); > > + /* Check if AFBC decoder is required for this buffer */ > + if ((meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || > + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) && > + fb->modifier & DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS)) > + priv->viu.osd1_afbcd = true; > + else > + priv->viu.osd1_afbcd = false; > + > /* Enable OSD and BLK0, set max global alpha */ > priv->viu.osd1_ctrl_stat = OSD_ENABLE | > (0xFF << OSD_GLOBAL_ALPHA_SHIFT) | > OSD_BLK0_ENABLE; > > + priv->viu.osd1_ctrl_stat2 = readl(priv->io_base + > + _REG(VIU_OSD1_CTRL_STAT2)); > + > canvas_id_osd1 = priv->canvas_id_osd1; > > /* Set up BLK0 to point to the right canvas */ > - priv->viu.osd1_blk0_cfg[0] = ((canvas_id_osd1 << OSD_CANVAS_SEL) | > - OSD_ENDIANNESS_LE); > + priv->viu.osd1_blk0_cfg[0] = canvas_id_osd1 << OSD_CANVAS_SEL; > + > + if (priv->viu.osd1_afbcd) { > + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { > + /* This is the internal decoding memory address */ > + priv->viu.osd1_blk1_cfg4 = MESON_G12A_AFBCD_OUT_ADDR; > + priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_BE; > + priv->viu.osd1_ctrl_stat2 |= OSD_PENDING_STAT_CLEAN; > + } > + > + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) { > + priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE; > + priv->viu.osd1_ctrl_stat2 |= OSD_DPATH_MALI_AFBCD; > + } > + } else { > + priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE; > + > + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) > + priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD; > + } > > /* On GXBB, Use the old non-HDR RGB2YUV converter */ > if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) > priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; > > + if (priv->viu.osd1_afbcd && > + meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { > + priv->viu.osd1_blk0_cfg[0] |= OSD_MALI_SRC_EN | > + priv->afbcd.ops->fmt_to_blk_mode(fb->modifier, > + fb->format->format); > + } else { > + switch (fb->format->format) { > + case DRM_FORMAT_XRGB8888: > + case DRM_FORMAT_ARGB8888: > + priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > + OSD_COLOR_MATRIX_32_ARGB; > + break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > + OSD_COLOR_MATRIX_32_ABGR; > + break; > + case DRM_FORMAT_RGB888: > + priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 | > + OSD_COLOR_MATRIX_24_RGB; > + break; > + case DRM_FORMAT_RGB565: > + priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 | > + OSD_COLOR_MATRIX_16_RGB565; > + break; > + }; > + } > + > switch (fb->format->format) { > case DRM_FORMAT_XRGB8888: > - /* For XRGB, replace the pixel's alpha by 0xFF */ > - writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, > - priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > - OSD_COLOR_MATRIX_32_ARGB; > - break; > case DRM_FORMAT_XBGR8888: > /* For XRGB, replace the pixel's alpha by 0xFF */ > - writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, > - priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > - OSD_COLOR_MATRIX_32_ABGR; > + priv->viu.osd1_ctrl_stat2 |= OSD_REPLACE_EN; > break; > case DRM_FORMAT_ARGB8888: > - /* For ARGB, use the pixel's alpha */ > - writel_bits_relaxed(OSD_REPLACE_EN, 0, > - priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > - OSD_COLOR_MATRIX_32_ARGB; > - break; > case DRM_FORMAT_ABGR8888: > /* For ARGB, use the pixel's alpha */ > - writel_bits_relaxed(OSD_REPLACE_EN, 0, > - priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | > - OSD_COLOR_MATRIX_32_ABGR; > - break; > - case DRM_FORMAT_RGB888: > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 | > - OSD_COLOR_MATRIX_24_RGB; > - break; > - case DRM_FORMAT_RGB565: > - priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 | > - OSD_COLOR_MATRIX_16_RGB565; > + priv->viu.osd1_ctrl_stat2 &= ~OSD_REPLACE_EN; > break; > }; > > @@ -307,6 +365,16 @@ static void meson_plane_atomic_update(struct drm_plane *plane, > priv->viu.osd1_height = fb->height; > priv->viu.osd1_width = fb->width; > > + if (priv->viu.osd1_afbcd) { > + priv->afbcd.modifier = fb->modifier; > + priv->afbcd.format = fb->format->format; > + > + /* Calculate decoder write stride */ > + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) > + priv->viu.osd1_blk2_cfg4 = > + meson_g12a_afbcd_line_stride(priv); > + } > + > if (!meson_plane->enabled) { > /* Reset OSD1 before enabling it on GXL+ SoCs */ > if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || > @@ -346,6 +414,42 @@ static const struct drm_plane_helper_funcs meson_plane_helper_funcs = { > .prepare_fb = drm_gem_fb_prepare_fb, > }; > > +static bool meson_plane_format_mod_supported(struct drm_plane *plane, > + u32 format, u64 modifier) > +{ > + struct meson_plane *meson_plane = to_meson_plane(plane); > + struct meson_drm *priv = meson_plane->priv; > + int i; > + > + if (modifier == DRM_FORMAT_MOD_INVALID) > + return false; > + > + if (modifier == DRM_FORMAT_MOD_LINEAR) > + return true; > + > + if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) && > + !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) > + return false; > + > + if (modifier & ~DRM_FORMAT_MOD_ARM_AFBC(MESON_MOD_AFBC_VALID_BITS)) > + return false; > + > + for (i = 0 ; i < plane->modifier_count ; ++i) > + if (plane->modifiers[i] == modifier) > + break; > + > + if (i == plane->modifier_count) { > + DRM_DEBUG_KMS("Unsupported modifier\n"); > + return false; > + } > + > + if (priv->afbcd.ops && priv->afbcd.ops->supported_fmt) > + return priv->afbcd.ops->supported_fmt(modifier, format); > + > + DRM_DEBUG_KMS("AFBC Unsupported\n"); > + return false; > +} > + > static const struct drm_plane_funcs meson_plane_funcs = { > .update_plane = drm_atomic_helper_update_plane, > .disable_plane = drm_atomic_helper_disable_plane, > @@ -353,6 +457,7 @@ static const struct drm_plane_funcs meson_plane_funcs = { > .reset = drm_atomic_helper_plane_reset, > .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, > .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, > + .format_mod_supported = meson_plane_format_mod_supported, > }; > > static const uint32_t supported_drm_formats[] = { > @@ -364,10 +469,53 @@ static const uint32_t supported_drm_formats[] = { > DRM_FORMAT_RGB565, > }; > > +static const uint64_t format_modifiers_afbc_gxm[] = { > + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > + AFBC_FORMAT_MOD_SPARSE | > + AFBC_FORMAT_MOD_YTR), > + /* SPLIT mandates SPARSE, RGB modes mandates YTR */ > + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > + AFBC_FORMAT_MOD_YTR | > + AFBC_FORMAT_MOD_SPARSE | > + AFBC_FORMAT_MOD_SPLIT), > + DRM_FORMAT_MOD_LINEAR, > + DRM_FORMAT_MOD_INVALID, > +}; > + > +static const uint64_t format_modifiers_afbc_g12a[] = { > + /* > + * - TOFIX Support AFBC modifiers for YUV formats (16x16 + TILED) > + * - AFBC_FORMAT_MOD_YTR is mandatory since we only support RGB > + * - SPLIT is mandatory for performances reasons when in 16x16 > + * block size > + * - 32x8 block size + SPLIT is mandatory with 4K frame size > + * for performances reasons > + */ > + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | > + AFBC_FORMAT_MOD_YTR | > + AFBC_FORMAT_MOD_SPARSE | > + AFBC_FORMAT_MOD_SPLIT), > + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | > + AFBC_FORMAT_MOD_YTR | > + AFBC_FORMAT_MOD_SPARSE), > + DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | > + AFBC_FORMAT_MOD_YTR | > + AFBC_FORMAT_MOD_SPARSE | > + AFBC_FORMAT_MOD_SPLIT), > + DRM_FORMAT_MOD_LINEAR, > + DRM_FORMAT_MOD_INVALID, > +}; > + > +static const uint64_t format_modifiers_default[] = { > + DRM_FORMAT_MOD_LINEAR, > + DRM_FORMAT_MOD_INVALID, > +}; > + > int meson_plane_create(struct meson_drm *priv) > { > struct meson_plane *meson_plane; > struct drm_plane *plane; > + const uint64_t *format_modifiers = format_modifiers_default; > > meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), > GFP_KERNEL); > @@ -377,11 +525,16 @@ int meson_plane_create(struct meson_drm *priv) > meson_plane->priv = priv; > plane = &meson_plane->base; > > + if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) > + format_modifiers = format_modifiers_afbc_gxm; > + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) > + format_modifiers = format_modifiers_afbc_g12a; > + > drm_universal_plane_init(priv->drm, plane, 0xFF, > &meson_plane_funcs, > supported_drm_formats, > ARRAY_SIZE(supported_drm_formats), > - NULL, > + format_modifiers, > DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); > > drm_plane_helper_add(plane, &meson_plane_helper_funcs); > -- > 2.22.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ayan Halder Subject: Re: [PATCH 4/7] drm/meson: plane: add support for AFBC mode for OSD1 plane Date: Thu, 10 Oct 2019 13:26:02 +0000 Message-ID: <20191010132601.GA10110@arm.com> References: <20191010092526.10419-1-narmstrong@baylibre.com> <20191010092526.10419-5-narmstrong@baylibre.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from EUR02-AM5-obe.outbound.protection.outlook.com (mail-eopbgr00082.outbound.protection.outlook.com [40.107.0.82]) by gabe.freedesktop.org (Postfix) with ESMTPS id 758186EB3A for ; Thu, 10 Oct 2019 13:26:17 +0000 (UTC) In-Reply-To: <20191010092526.10419-5-narmstrong@baylibre.com> Content-Language: en-US Content-ID: <409F2695D4D3D64EBD6188B8899ECDB1@eurprd08.prod.outlook.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Neil Armstrong Cc: "khilman@baylibre.com" , nd , "linux-arm-kernel@lists.infradead.org" , "dri-devel@lists.freedesktop.org" , "linux-amlogic@lists.infradead.org" List-Id: dri-devel@lists.freedesktop.org T24gVGh1LCBPY3QgMTAsIDIwMTkgYXQgMTE6MjU6MjNBTSArMDIwMCwgTmVpbCBBcm1zdHJvbmcg d3JvdGU6Cj4gVGhpcyBhZGRzIGFsbCB0aGUgT1NEIGNvbmZpZ3VyYXRpb24gcGx1bWJpbmcgdG8g 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