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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/4] drm/i915/display: Check if FBC and DMC are fused off
Date: Fri, 11 Oct 2019 15:29:29 +0300	[thread overview]
Message-ID: <20191011122929.GQ1208@intel.com> (raw)
In-Reply-To: <20191010193241.101401-4-jose.souza@intel.com>

On Thu, Oct 10, 2019 at 12:32:41PM -0700, José Roberto de Souza wrote:
> Those features could be fused off on GEN9 non-low power and newer
> GENs.

Should probably be two patches.

> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 2 ++
>  drivers/gpu/drm/i915/intel_device_info.c | 6 ++++++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 39c65f051468..086a8e6e86f1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7643,7 +7643,9 @@ enum {
>  #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
>  
>  #define SKL_DFSM			_MMIO(0x51000)
> +#define SKL_DFSM_DISPLAY_PM_DISABLE	(1 << 27)

Looks correct.

>  #define SKL_DFSM_DISPLAY_HDCP_DISABLE	(1 << 25)
> +#define SKL_DFSM_DMC_DISABLE		(1 << 23)

That seems to be a thing for icl+ only.

>  #define BXT_DFSM_CDCLK_LIMIT_MASK	(3 << 23)
>  #define BXT_DFSM_CDCLK_LIMIT_675	(0 << 23)
>  #define BXT_DFSM_CDCLK_LIMIT_540	(1 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index 5cfa197090e2..deeab3790a51 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -983,6 +983,12 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>  
>  		if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
>  			info->display.has_hdcp = 0;
> +
> +		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
> +			info->display.has_fbc = 0;
> +
> +		if (!IS_GEN9_BC(dev_priv) && dfsm & SKL_DFSM_DMC_DISABLE)
> +			info->display.has_csr = 0;
>  	}
>  
>  	/* Initialize slice/subslice/EU info */
> -- 
> 2.23.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-10-11 12:29 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-10 19:32 [PATCH 1/4] drm/i915/display: Handle fused off display correctly José Roberto de Souza
2019-10-10 19:32 ` [PATCH 2/4] drm/i915/display: Handle fused off HDCP José Roberto de Souza
2019-10-11 12:27   ` Ville Syrjälä
2019-10-10 19:32 ` [PATCH 3/4] drm/i915/display: DFSM CDCLK LIMIT is only available in BXT José Roberto de Souza
2019-10-10 20:45   ` Souza, Jose
2019-10-11 12:31     ` Ville Syrjälä
2019-10-10 19:32 ` [PATCH 4/4] drm/i915/display: Check if FBC and DMC are fused off José Roberto de Souza
2019-10-11 12:29   ` Ville Syrjälä [this message]
2019-10-10 20:18 ` ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Handle fused off display correctly Patchwork
2019-10-11  7:16   ` Martin Peres
2019-10-11 19:30     ` Souza, Jose
2019-10-11 12:25 ` [PATCH 1/4] " Ville Syrjälä
2019-10-11 15:00   ` Souza, Jose

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