From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 24DC7ECE588 for ; Tue, 15 Oct 2019 16:29:24 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id F3CE62086A for ; Tue, 15 Oct 2019 16:29:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org F3CE62086A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iKPhD-0003WO-01; Tue, 15 Oct 2019 16:29:14 +0000 Received: from us1-rack-iad1.inumbo.com ([172.99.69.81]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iKPhB-0003Vm-Gi for xen-devel@lists.xenproject.org; Tue, 15 Oct 2019 16:29:13 +0000 X-Inumbo-ID: ec10cf36-ef68-11e9-beca-bc764e2007e4 Received: from mx1.redhat.com (unknown [209.132.183.28]) by us1-rack-iad1.inumbo.com (Halon) with ESMTPS id ec10cf36-ef68-11e9-beca-bc764e2007e4; Tue, 15 Oct 2019 16:29:13 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7E8ED307D942; Tue, 15 Oct 2019 16:29:12 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-35.brq.redhat.com [10.40.204.35]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 21B2419C58; Tue, 15 Oct 2019 16:29:05 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 15 Oct 2019 18:26:42 +0200 Message-Id: <20191015162705.28087-10-philmd@redhat.com> In-Reply-To: <20191015162705.28087-1-philmd@redhat.com> References: <20191015162705.28087-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Tue, 15 Oct 2019 16:29:12 +0000 (UTC) Subject: [Xen-devel] [PATCH 09/32] piix4: add Reset Control Register X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Stefano Stabellini , Eduardo Habkost , kvm@vger.kernel.org, Paul Durrant , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Markovic , xen-devel@lists.xenproject.org, Anthony Perard , Igor Mammedov , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" RnJvbTogSGVydsOpIFBvdXNzaW5lYXUgPGhwb3Vzc2luQHJlYWN0b3Mub3JnPgoKVGhlIFJDUiBJ L08gcG9ydCAoMHhjZjkpIGlzIHVzZWQgdG8gZ2VuZXJhdGUgYSBoYXJkIHJlc2V0IG9yIGEgc29m dCByZXNldC4KCkFja2VkLWJ5OiBNaWNoYWVsIFMuIFRzaXJraW4gPG1zdEByZWRoYXQuY29tPgpB Y2tlZC1ieTogUGFvbG8gQm9uemluaSA8cGJvbnppbmlAcmVkaGF0LmNvbT4KU2lnbmVkLW9mZi1i eTogSGVydsOpIFBvdXNzaW5lYXUgPGhwb3Vzc2luQHJlYWN0b3Mub3JnPgpNZXNzYWdlLUlkOiA8 MjAxNzEyMTYwOTAyMjguMjg1MDUtNy1ocG91c3NpbkByZWFjdG9zLm9yZz4KW1BNRDogcmViYXNl ZCwgdXBkYXRlZCBpbmNsdWRlc10KU2lnbmVkLW9mZi1ieTogUGhpbGlwcGUgTWF0aGlldS1EYXVk w6kgPHBoaWxtZEByZWRoYXQuY29tPgotLS0KIGh3L2lzYS9waWl4NC5jIHwgNDAgKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKwogMSBmaWxlIGNoYW5nZWQsIDQwIGluc2Vy dGlvbnMoKykKCmRpZmYgLS1naXQgYS9ody9pc2EvcGlpeDQuYyBiL2h3L2lzYS9waWl4NC5jCmlu ZGV4IDQyMDIyNDNlNDEuLjZlMmQ5Yjk3NzQgMTAwNjQ0Ci0tLSBhL2h3L2lzYS9waWl4NC5jCisr KyBiL2h3L2lzYS9waWl4NC5jCkBAIC0yLDYgKzIsNyBAQAogICogUUVNVSBQSUlYNCBQQ0kgQnJp ZGdlIEVtdWxhdGlvbgogICoKICAqIENvcHlyaWdodCAoYykgMjAwNiBGYWJyaWNlIEJlbGxhcmQK KyAqIENvcHlyaWdodCAoYykgMjAxOCBIZXJ2w6kgUG91c3NpbmVhdQogICoKICAqIFBlcm1pc3Np b24gaXMgaGVyZWJ5IGdyYW50ZWQsIGZyZWUgb2YgY2hhcmdlLCB0byBhbnkgcGVyc29uIG9idGFp bmluZyBhIGNvcHkKICAqIG9mIHRoaXMgc29mdHdhcmUgYW5kIGFzc29jaWF0ZWQgZG9jdW1lbnRh dGlvbiBmaWxlcyAodGhlICJTb2Z0d2FyZSIpLCB0byBkZWFsCkBAIC0yOSwxMSArMzAsMTYgQEAK ICNpbmNsdWRlICJody9zeXNidXMuaCIKICNpbmNsdWRlICJtaWdyYXRpb24vdm1zdGF0ZS5oIgog I2luY2x1ZGUgInN5c2VtdS9yZXNldC5oIgorI2luY2x1ZGUgInN5c2VtdS9ydW5zdGF0ZS5oIgog CiBQQ0lEZXZpY2UgKnBpaXg0X2RldjsKIAogdHlwZWRlZiBzdHJ1Y3QgUElJWDRTdGF0ZSB7CiAg ICAgUENJRGV2aWNlIGRldjsKKworICAgIC8qIFJlc2V0IENvbnRyb2wgUmVnaXN0ZXIgKi8KKyAg ICBNZW1vcnlSZWdpb24gcmNyX21lbTsKKyAgICB1aW50OF90IHJjcjsKIH0gUElJWDRTdGF0ZTsK IAogI2RlZmluZSBUWVBFX1BJSVg0X1BDSV9ERVZJQ0UgIlBJSVg0IgpAQCAtODgsNiArOTQsMzQg QEAgc3RhdGljIGNvbnN0IFZNU3RhdGVEZXNjcmlwdGlvbiB2bXN0YXRlX3BpaXg0ID0gewogICAg IH0KIH07CiAKK3N0YXRpYyB2b2lkIHBpaXg0X3Jjcl93cml0ZSh2b2lkICpvcGFxdWUsIGh3YWRk ciBhZGRyLCB1aW50NjRfdCB2YWwsCisgICAgICAgICAgICAgICAgICAgICAgICAgICAgdW5zaWdu ZWQgaW50IGxlbikKK3sKKyAgICBQSUlYNFN0YXRlICpzID0gb3BhcXVlOworCisgICAgaWYgKHZh bCAmIDQpIHsKKyAgICAgICAgcWVtdV9zeXN0ZW1fcmVzZXRfcmVxdWVzdChTSFVURE9XTl9DQVVT RV9HVUVTVF9SRVNFVCk7CisgICAgICAgIHJldHVybjsKKyAgICB9CisgICAgcy0+cmNyID0gdmFs ICYgMjsgLyoga2VlcCBTeXN0ZW0gUmVzZXQgdHlwZSBvbmx5ICovCit9CisKK3N0YXRpYyB1aW50 NjRfdCBwaWl4NF9yY3JfcmVhZCh2b2lkICpvcGFxdWUsIGh3YWRkciBhZGRyLCB1bnNpZ25lZCBp bnQgbGVuKQoreworICAgIFBJSVg0U3RhdGUgKnMgPSBvcGFxdWU7CisgICAgcmV0dXJuIHMtPnJj cjsKK30KKworc3RhdGljIGNvbnN0IE1lbW9yeVJlZ2lvbk9wcyBwaWl4NF9yY3Jfb3BzID0gewor ICAgIC5yZWFkID0gcGlpeDRfcmNyX3JlYWQsCisgICAgLndyaXRlID0gcGlpeDRfcmNyX3dyaXRl LAorICAgIC5lbmRpYW5uZXNzID0gREVWSUNFX0xJVFRMRV9FTkRJQU4sCisgICAgLmltcGwgPSB7 CisgICAgICAgIC5taW5fYWNjZXNzX3NpemUgPSAxLAorICAgICAgICAubWF4X2FjY2Vzc19zaXpl ID0gMSwKKyAgICB9LAorfTsKKwogc3RhdGljIHZvaWQgcGlpeDRfcmVhbGl6ZShQQ0lEZXZpY2Ug KnBjaV9kZXYsIEVycm9yICoqZXJycCkKIHsKICAgICBEZXZpY2VTdGF0ZSAqZGV2ID0gREVWSUNF KHBjaV9kZXYpOwpAQCAtOTcsNiArMTMxLDEyIEBAIHN0YXRpYyB2b2lkIHBpaXg0X3JlYWxpemUo UENJRGV2aWNlICpwY2lfZGV2LCBFcnJvciAqKmVycnApCiAgICAgICAgICAgICAgICAgICAgICBw Y2lfYWRkcmVzc19zcGFjZV9pbyhwY2lfZGV2KSwgZXJycCkpIHsKICAgICAgICAgcmV0dXJuOwog ICAgIH0KKworICAgIG1lbW9yeV9yZWdpb25faW5pdF9pbygmcy0+cmNyX21lbSwgT0JKRUNUKGRl diksICZwaWl4NF9yY3Jfb3BzLCBzLAorICAgICAgICAgICAgICAgICAgICAgICAgICAicmVzZXQt Y29udHJvbCIsIDEpOworICAgIG1lbW9yeV9yZWdpb25fYWRkX3N1YnJlZ2lvbl9vdmVybGFwKHBj aV9hZGRyZXNzX3NwYWNlX2lvKHBjaV9kZXYpLCAweGNmOSwKKyAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAmcy0+cmNyX21lbSwgMSk7CisKICAgICBwaWl4NF9kZXYgPSBw Y2lfZGV2OwogICAgIHFlbXVfcmVnaXN0ZXJfcmVzZXQocGlpeDRfcmVzZXQsIHMpOwogfQotLSAK Mi4yMS4wCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18K WGVuLWRldmVsIG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVucHJvamVjdC5vcmcKaHR0 cHM6Ly9saXN0cy54ZW5wcm9qZWN0Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL3hlbi1kZXZlbA== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3650BECE588 for ; Tue, 15 Oct 2019 16:29:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 15B732086A for ; Tue, 15 Oct 2019 16:29:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387864AbfJOQ3N (ORCPT ); Tue, 15 Oct 2019 12:29:13 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47044 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732717AbfJOQ3N (ORCPT ); Tue, 15 Oct 2019 12:29:13 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 7E8ED307D942; Tue, 15 Oct 2019 16:29:12 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-35.brq.redhat.com [10.40.204.35]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 21B2419C58; Tue, 15 Oct 2019 16:29:05 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Aleksandar Markovic , Aurelien Jarno , Eduardo Habkost , Thomas Huth , Igor Mammedov , Anthony Perard , Stefano Stabellini , Paul Durrant , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Rikalo , xen-devel@lists.xenproject.org, Laurent Vivier , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 09/32] piix4: add Reset Control Register Date: Tue, 15 Oct 2019 18:26:42 +0200 Message-Id: <20191015162705.28087-10-philmd@redhat.com> In-Reply-To: <20191015162705.28087-1-philmd@redhat.com> References: <20191015162705.28087-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Tue, 15 Oct 2019 16:29:12 +0000 (UTC) Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Hervé Poussineau The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-7-hpoussin@reactos.org> [PMD: rebased, updated includes] Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 4202243e41..6e2d9b9774 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -2,6 +2,7 @@ * QEMU PIIX4 PCI Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Hervé Poussineau * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -29,11 +30,16 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "sysemu/reset.h" +#include "sysemu/runstate.h" PCIDevice *piix4_dev; typedef struct PIIX4State { PCIDevice dev; + + /* Reset Control Register */ + MemoryRegion rcr_mem; + uint8_t rcr; } PIIX4State; #define TYPE_PIIX4_PCI_DEVICE "PIIX4" @@ -88,6 +94,34 @@ static const VMStateDescription vmstate_piix4 = { } }; +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int len) +{ + PIIX4State *s = opaque; + + if (val & 4) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + } + s->rcr = val & 2; /* keep System Reset type only */ +} + +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len) +{ + PIIX4State *s = opaque; + return s->rcr; +} + +static const MemoryRegionOps piix4_rcr_ops = { + .read = piix4_rcr_read, + .write = piix4_rcr_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + static void piix4_realize(PCIDevice *pci_dev, Error **errp) { DeviceState *dev = DEVICE(pci_dev); @@ -97,6 +131,12 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp) pci_address_space_io(pci_dev), errp)) { return; } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xcf9, + &s->rcr_mem, 1); + piix4_dev = pci_dev; qemu_register_reset(piix4_reset, s); } -- 2.21.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83E97C10F14 for ; Tue, 15 Oct 2019 16:39:11 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5506320650 for ; Tue, 15 Oct 2019 16:39:11 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5506320650 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; 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Tue, 15 Oct 2019 16:29:12 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-35.brq.redhat.com [10.40.204.35]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 21B2419C58; Tue, 15 Oct 2019 16:29:05 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 09/32] piix4: add Reset Control Register Date: Tue, 15 Oct 2019 18:26:42 +0200 Message-Id: <20191015162705.28087-10-philmd@redhat.com> In-Reply-To: <20191015162705.28087-1-philmd@redhat.com> References: <20191015162705.28087-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Tue, 15 Oct 2019 16:29:12 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Stefano Stabellini , Eduardo Habkost , kvm@vger.kernel.org, Paul Durrant , "Michael S. Tsirkin" , Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Markovic , xen-devel@lists.xenproject.org, Anthony Perard , Igor Mammedov , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Herv=C3=A9 Poussineau The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset= . Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Herv=C3=A9 Poussineau Message-Id: <20171216090228.28505-7-hpoussin@reactos.org> [PMD: rebased, updated includes] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/piix4.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 4202243e41..6e2d9b9774 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -2,6 +2,7 @@ * QEMU PIIX4 PCI Bridge Emulation * * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2018 Herv=C3=A9 Poussineau * * Permission is hereby granted, free of charge, to any person obtaining= a copy * of this software and associated documentation files (the "Software"),= to deal @@ -29,11 +30,16 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "sysemu/reset.h" +#include "sysemu/runstate.h" =20 PCIDevice *piix4_dev; =20 typedef struct PIIX4State { PCIDevice dev; + + /* Reset Control Register */ + MemoryRegion rcr_mem; + uint8_t rcr; } PIIX4State; =20 #define TYPE_PIIX4_PCI_DEVICE "PIIX4" @@ -88,6 +94,34 @@ static const VMStateDescription vmstate_piix4 =3D { } }; =20 +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int len) +{ + PIIX4State *s =3D opaque; + + if (val & 4) { + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; + } + s->rcr =3D val & 2; /* keep System Reset type only */ +} + +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int l= en) +{ + PIIX4State *s =3D opaque; + return s->rcr; +} + +static const MemoryRegionOps piix4_rcr_ops =3D { + .read =3D piix4_rcr_read, + .write =3D piix4_rcr_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 1, + .max_access_size =3D 1, + }, +}; + static void piix4_realize(PCIDevice *pci_dev, Error **errp) { DeviceState *dev =3D DEVICE(pci_dev); @@ -97,6 +131,12 @@ static void piix4_realize(PCIDevice *pci_dev, Error *= *errp) pci_address_space_io(pci_dev), errp)) { return; } + + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, + "reset-control", 1); + memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0= xcf9, + &s->rcr_mem, 1); + piix4_dev =3D pci_dev; qemu_register_reset(piix4_reset, s); } --=20 2.21.0