From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8662DECE58F for ; Tue, 15 Oct 2019 16:29:37 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5FC982086A for ; Tue, 15 Oct 2019 16:29:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5FC982086A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iKPhO-0003bt-93; Tue, 15 Oct 2019 16:29:26 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iKPhN-0003bE-1a for xen-devel@lists.xenproject.org; Tue, 15 Oct 2019 16:29:25 +0000 X-Inumbo-ID: f2eaa5b6-ef68-11e9-9396-12813bfff9fa Received: from mx1.redhat.com (unknown [209.132.183.28]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id f2eaa5b6-ef68-11e9-9396-12813bfff9fa; Tue, 15 Oct 2019 16:29:24 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EFC2918C8936; Tue, 15 Oct 2019 16:29:23 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-35.brq.redhat.com [10.40.204.35]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1003719C58; Tue, 15 Oct 2019 16:29:12 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Tue, 15 Oct 2019 18:26:43 +0200 Message-Id: <20191015162705.28087-11-philmd@redhat.com> In-Reply-To: <20191015162705.28087-1-philmd@redhat.com> References: <20191015162705.28087-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.70]); Tue, 15 Oct 2019 16:29:24 +0000 (UTC) Subject: [Xen-devel] [PATCH 10/32] piix4: add a i8259 interrupt controller as specified in datasheet X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Stefano Stabellini , Eduardo Habkost , kvm@vger.kernel.org, Paul Durrant , "Michael S. Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Markovic , xen-devel@lists.xenproject.org, Anthony Perard , Igor Mammedov , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" RnJvbTogSGVydsOpIFBvdXNzaW5lYXUgPGhwb3Vzc2luQHJlYWN0b3Mub3JnPgoKQWRkIElTQSBp cnFzIGFzIHBpaXg0IGdwaW8gaW4sIGFuZCBDUFUgaW50ZXJydXB0IHJlcXVlc3QgYXMgcGlpeDQg Z3BpbyBvdXQuClJlbW92ZSBpODI1OSBpbnN0YW5jaWF0ZWQgaW4gbWFsdGEgYm9hcmQsIHRvIG5v dCBoYXZlIGl0IHR3aWNlLgoKV2UgY2FuIGFsc28gcmVtb3ZlIHRoZSBub3cgdW51c2VkIHBpaXg0 X2luaXQoKSBmdW5jdGlvbi4KCkFja2VkLWJ5OiBNaWNoYWVsIFMuIFRzaXJraW4gPG1zdEByZWRo YXQuY29tPgpBY2tlZC1ieTogUGFvbG8gQm9uemluaSA8cGJvbnppbmlAcmVkaGF0LmNvbT4KU2ln bmVkLW9mZi1ieTogSGVydsOpIFBvdXNzaW5lYXUgPGhwb3Vzc2luQHJlYWN0b3Mub3JnPgpNZXNz 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Tsirkin" , Marcel Apfelbaum , Paolo Bonzini , Richard Henderson , kvm@vger.kernel.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 10/32] piix4: add a i8259 interrupt controller as specified in datasheet Date: Tue, 15 Oct 2019 18:26:43 +0200 Message-Id: <20191015162705.28087-11-philmd@redhat.com> In-Reply-To: <20191015162705.28087-1-philmd@redhat.com> References: <20191015162705.28087-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.70]); Tue, 15 Oct 2019 16:29:24 +0000 (UTC) Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Hervé Poussineau Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out. Remove i8259 instanciated in malta board, to not have it twice. We can also remove the now unused piix4_init() function. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Hervé Poussineau Message-Id: <20171216090228.28505-8-hpoussin@reactos.org> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop] Signed-off-by: Philippe Mathieu-Daudé --- hw/isa/piix4.c | 41 ++++++++++++++++++++++++++++++----------- hw/mips/mips_malta.c | 32 +++++++++++++------------------- include/hw/i386/pc.h | 1 - 3 files changed, 43 insertions(+), 31 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 6e2d9b9774..1cfc51335a 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -24,6 +24,7 @@ */ #include "qemu/osdep.h" +#include "hw/irq.h" #include "hw/i386/pc.h" #include "hw/pci/pci.h" #include "hw/isa/isa.h" @@ -36,6 +37,8 @@ PCIDevice *piix4_dev; typedef struct PIIX4State { PCIDevice dev; + qemu_irq cpu_intr; + qemu_irq *isa; /* Reset Control Register */ MemoryRegion rcr_mem; @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = { } }; +static void piix4_request_i8259_irq(void *opaque, int irq, int level) +{ + PIIX4State *s = opaque; + qemu_set_irq(s->cpu_intr, level); +} + +static void piix4_set_i8259_irq(void *opaque, int irq, int level) +{ + PIIX4State *s = opaque; + qemu_set_irq(s->isa[irq], level); +} + static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -126,30 +141,34 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp) { DeviceState *dev = DEVICE(pci_dev); PIIX4State *s = DO_UPCAST(PIIX4State, dev, pci_dev); + ISABus *isa_bus; + qemu_irq *i8259_out_irq; - if (!isa_bus_new(dev, pci_address_space(pci_dev), - pci_address_space_io(pci_dev), errp)) { + isa_bus = isa_bus_new(dev, pci_address_space(pci_dev), + pci_address_space_io(pci_dev), errp); + if (!isa_bus) { return; } + qdev_init_gpio_in_named(dev, piix4_set_i8259_irq, "isa", ISA_NUM_IRQS); + qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1); + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xcf9, &s->rcr_mem, 1); + /* initialize i8259 pic */ + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); + s->isa = i8259_init(isa_bus, *i8259_out_irq); + + /* initialize ISA irqs */ + isa_bus_irqs(isa_bus, s->isa); + piix4_dev = pci_dev; qemu_register_reset(piix4_reset, s); } -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn) -{ - PCIDevice *d; - - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4"); - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); - return d->devfn; -} - static void piix4_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 4d9c64b36a..7d25ab6c23 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -97,7 +97,7 @@ typedef struct { SysBusDevice parent_obj; MIPSCPSState cps; - qemu_irq *i8259; + qemu_irq i8259[16]; } MaltaState; static ISADevice *pit; @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine) int64_t kernel_entry, bootloader_run_addr; PCIBus *pci_bus; ISABus *isa_bus; - qemu_irq *isa_irq; qemu_irq cbus_irq, i8259_irq; + PCIDevice *pci; int piix4_devfn; I2CBus *smbus; DriveInfo *dinfo; @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine) /* Board ID = 0x420 (Malta Board with CoreLV) */ stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); - /* - * We have a circular dependency problem: pci_bus depends on isa_irq, - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends - * on piix4, and piix4 depends on pci_bus. To stop the cycle we have - * qemu_irq_proxy() adds an extra bit of indirection, allowing us - * to resolve the isa_irq -> i8259 dependency after i8259 is initialized. - */ - isa_irq = qemu_irq_proxy(&s->i8259, 16); - /* Northbridge */ - pci_bus = gt64120_register(isa_irq); + pci_bus = gt64120_register(s->i8259); /* Southbridge */ ide_drive_get(hd, ARRAY_SIZE(hd)); - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80); + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), + true, "PIIX4"); + dev = DEVICE(pci); + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); + piix4_devfn = pci->devfn; - /* - * Interrupt controller - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 - */ - s->i8259 = i8259_init(isa_bus, i8259_irq); + /* Interrupt controller */ + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); + for (int i = 0; i < ISA_NUM_IRQS; i++) { + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i); + } - isa_bus_irqs(isa_bus, s->i8259); pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1); pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci"); smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 09e74e7764..a95eab0d8a 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -282,7 +282,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type, PCIBus *find_i440fx(void); /* piix4.c */ extern PCIDevice *piix4_dev; -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); /* pc_sysfw.c */ void pc_system_flash_create(PCMachineState *pcms); -- 2.21.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNWANTED_LANGUAGE_BODY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9BA1AECE588 for ; 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Tue, 15 Oct 2019 12:29:26 -0400 Received: from mx1.redhat.com ([209.132.183.28]:12096) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iKPhM-00051q-RV for qemu-devel@nongnu.org; Tue, 15 Oct 2019 12:29:25 -0400 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EFC2918C8936; Tue, 15 Oct 2019 16:29:23 +0000 (UTC) Received: from x1w.redhat.com (ovpn-204-35.brq.redhat.com [10.40.204.35]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1003719C58; Tue, 15 Oct 2019 16:29:12 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 10/32] piix4: add a i8259 interrupt controller as specified in datasheet Date: Tue, 15 Oct 2019 18:26:43 +0200 Message-Id: <20191015162705.28087-11-philmd@redhat.com> In-Reply-To: <20191015162705.28087-1-philmd@redhat.com> References: <20191015162705.28087-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.6.2 (mx1.redhat.com [10.5.110.70]); Tue, 15 Oct 2019 16:29:24 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Stefano Stabellini , Eduardo Habkost , kvm@vger.kernel.org, Paul Durrant , "Michael S. Tsirkin" , Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Markovic , xen-devel@lists.xenproject.org, Anthony Perard , Igor Mammedov , Aleksandar Rikalo , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Richard Henderson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Herv=C3=A9 Poussineau Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio ou= t. Remove i8259 instanciated in malta board, to not have it twice. We can also remove the now unused piix4_init() function. Acked-by: Michael S. Tsirkin Acked-by: Paolo Bonzini Signed-off-by: Herv=C3=A9 Poussineau Message-Id: <20171216090228.28505-8-hpoussin@reactos.org> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/isa/piix4.c | 41 ++++++++++++++++++++++++++++++----------- hw/mips/mips_malta.c | 32 +++++++++++++------------------- include/hw/i386/pc.h | 1 - 3 files changed, 43 insertions(+), 31 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 6e2d9b9774..1cfc51335a 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -24,6 +24,7 @@ */ =20 #include "qemu/osdep.h" +#include "hw/irq.h" #include "hw/i386/pc.h" #include "hw/pci/pci.h" #include "hw/isa/isa.h" @@ -36,6 +37,8 @@ PCIDevice *piix4_dev; =20 typedef struct PIIX4State { PCIDevice dev; + qemu_irq cpu_intr; + qemu_irq *isa; =20 /* Reset Control Register */ MemoryRegion rcr_mem; @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 =3D { } }; =20 +static void piix4_request_i8259_irq(void *opaque, int irq, int level) +{ + PIIX4State *s =3D opaque; + qemu_set_irq(s->cpu_intr, level); +} + +static void piix4_set_i8259_irq(void *opaque, int irq, int level) +{ + PIIX4State *s =3D opaque; + qemu_set_irq(s->isa[irq], level); +} + static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned int len) { @@ -126,30 +141,34 @@ static void piix4_realize(PCIDevice *pci_dev, Error= **errp) { DeviceState *dev =3D DEVICE(pci_dev); PIIX4State *s =3D DO_UPCAST(PIIX4State, dev, pci_dev); + ISABus *isa_bus; + qemu_irq *i8259_out_irq; =20 - if (!isa_bus_new(dev, pci_address_space(pci_dev), - pci_address_space_io(pci_dev), errp)) { + isa_bus =3D isa_bus_new(dev, pci_address_space(pci_dev), + pci_address_space_io(pci_dev), errp); + if (!isa_bus) { return; } =20 + qdev_init_gpio_in_named(dev, piix4_set_i8259_irq, "isa", ISA_NUM_IRQ= S); + qdev_init_gpio_out_named(dev, &s->cpu_intr, "intr", 1); + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s, "reset-control", 1); memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0= xcf9, &s->rcr_mem, 1); =20 + /* initialize i8259 pic */ + i8259_out_irq =3D qemu_allocate_irqs(piix4_request_i8259_irq, s, 1); + s->isa =3D i8259_init(isa_bus, *i8259_out_irq); + + /* initialize ISA irqs */ + isa_bus_irqs(isa_bus, s->isa); + piix4_dev =3D pci_dev; qemu_register_reset(piix4_reset, s); } =20 -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn) -{ - PCIDevice *d; - - d =3D pci_create_simple_multifunction(bus, devfn, true, "PIIX4"); - *isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); - return d->devfn; -} - static void piix4_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 4d9c64b36a..7d25ab6c23 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -97,7 +97,7 @@ typedef struct { SysBusDevice parent_obj; =20 MIPSCPSState cps; - qemu_irq *i8259; + qemu_irq i8259[16]; } MaltaState; =20 static ISADevice *pit; @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine) int64_t kernel_entry, bootloader_run_addr; PCIBus *pci_bus; ISABus *isa_bus; - qemu_irq *isa_irq; qemu_irq cbus_irq, i8259_irq; + PCIDevice *pci; int piix4_devfn; I2CBus *smbus; DriveInfo *dinfo; @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine) /* Board ID =3D 0x420 (Malta Board with CoreLV) */ stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420); =20 - /* - * We have a circular dependency problem: pci_bus depends on isa_irq= , - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends - * on piix4, and piix4 depends on pci_bus. To stop the cycle we hav= e - * qemu_irq_proxy() adds an extra bit of indirection, allowing us - * to resolve the isa_irq -> i8259 dependency after i8259 is initial= ized. - */ - isa_irq =3D qemu_irq_proxy(&s->i8259, 16); - /* Northbridge */ - pci_bus =3D gt64120_register(isa_irq); + pci_bus =3D gt64120_register(s->i8259); =20 /* Southbridge */ ide_drive_get(hd, ARRAY_SIZE(hd)); =20 - piix4_devfn =3D piix4_init(pci_bus, &isa_bus, 80); + pci =3D pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), + true, "PIIX4"); + dev =3D DEVICE(pci); + isa_bus =3D ISA_BUS(qdev_get_child_bus(dev, "isa.0")); + piix4_devfn =3D pci->devfn; =20 - /* - * Interrupt controller - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 - */ - s->i8259 =3D i8259_init(isa_bus, i8259_irq); + /* Interrupt controller */ + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); + for (int i =3D 0; i < ISA_NUM_IRQS; i++) { + s->i8259[i] =3D qdev_get_gpio_in_named(dev, "isa", i); + } =20 - isa_bus_irqs(isa_bus, s->i8259); pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1); pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci"); smbus =3D piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 09e74e7764..a95eab0d8a 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -282,7 +282,6 @@ PCIBus *i440fx_init(const char *host_type, const char= *pci_type, PCIBus *find_i440fx(void); /* piix4.c */ extern PCIDevice *piix4_dev; -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); =20 /* pc_sysfw.c */ void pc_system_flash_create(PCMachineState *pcms); --=20 2.21.0