From: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [RFC PATCH v2 09/18] sdram: socfpga: gen5: make config structs dts compatible
Date: Tue, 15 Oct 2019 22:10:22 +0200 [thread overview]
Message-ID: <20191015201032.20156-10-simon.k.r.goldschmidt@gmail.com> (raw)
In-Reply-To: <20191015201032.20156-1-simon.k.r.goldschmidt@gmail.com>
In preparation of moving SDRAM config from 'qts' files to devicetree,
make the config structs compatible to devicetree by keeping all struct
members of the same type (u8 or u32). That way, these structs can be
stored to devicetree as simple array.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
---
Changes in v2: None
.../mach-socfpga/include/mach/sdram_gen5.h | 8 +++-
arch/arm/mach-socfpga/wrap_sdram_config.c | 8 +++-
drivers/ddr/altera/sequencer.c | 39 +++++++++++--------
3 files changed, 35 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
index c41208591a..7353b1c5e6 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram_gen5.h
@@ -180,7 +180,8 @@ struct socfpga_sdram_rw_mgr_config {
};
struct socfpga_sdram_io_config {
- u16 delay_per_opa_tap;
+ u8 delay_per_opa_tap_lo;
+ u8 delay_per_opa_tap_hi;
u8 delay_per_dchain_tap;
u8 delay_per_dqs_en_dchain_tap;
u8 dll_chain_length;
@@ -198,7 +199,10 @@ struct socfpga_sdram_io_config {
};
struct socfpga_sdram_misc_config {
- u32 reg_file_init_seq_signature;
+ u8 reg_file_init_seq_signature_ll;
+ u8 reg_file_init_seq_signature_lh;
+ u8 reg_file_init_seq_signature_hl;
+ u8 reg_file_init_seq_signature_hh;
u8 afi_rate_ratio;
u8 calib_lfifo_offset;
u8 calib_vfifo_offset;
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
index 2b072cc65e..c43c2423a0 100644
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -254,7 +254,8 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
static const struct socfpga_sdram_io_config io_config = {
.delay_per_dchain_tap = IO_DELAY_PER_DCHAIN_TAP,
.delay_per_dqs_en_dchain_tap = IO_DELAY_PER_DQS_EN_DCHAIN_TAP,
- .delay_per_opa_tap = IO_DELAY_PER_OPA_TAP,
+ .delay_per_opa_tap_lo = IO_DELAY_PER_OPA_TAP & 0xff,
+ .delay_per_opa_tap_hi = (IO_DELAY_PER_OPA_TAP << 8) & 0xff,
.dll_chain_length = IO_DLL_CHAIN_LENGTH,
.dqdqs_out_phase_max = IO_DQDQS_OUT_PHASE_MAX,
.dqs_en_delay_max = IO_DQS_EN_DELAY_MAX,
@@ -276,7 +277,10 @@ static const struct socfpga_sdram_misc_config misc_config = {
.enable_super_quick_calibration = ENABLE_SUPER_QUICK_CALIBRATION,
.max_latency_count_width = MAX_LATENCY_COUNT_WIDTH,
.read_valid_fifo_size = READ_VALID_FIFO_SIZE,
- .reg_file_init_seq_signature = REG_FILE_INIT_SEQ_SIGNATURE,
+ .reg_file_init_seq_signature_ll = REG_FILE_INIT_SEQ_SIGNATURE & 0xff,
+ .reg_file_init_seq_signature_lh = (REG_FILE_INIT_SEQ_SIGNATURE >> 8) & 0xff,
+ .reg_file_init_seq_signature_hl = (REG_FILE_INIT_SEQ_SIGNATURE >> 16) & 0xff,
+ .reg_file_init_seq_signature_hh = (REG_FILE_INIT_SEQ_SIGNATURE >> 24) & 0xff,
.tinit_cntr0_val = TINIT_CNTR0_VAL,
.tinit_cntr1_val = TINIT_CNTR1_VAL,
.tinit_cntr2_val = TINIT_CNTR2_VAL,
diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index b85b56efe5..6c632227c2 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -30,6 +30,9 @@ static const struct socfpga_data_mgr *data_mgr =
static const struct socfpga_sdr_ctrl *sdr_ctrl =
(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
+#define delay_per_opa_tap(iocfg) ((iocfg)->delay_per_opa_tap_lo | \
+ ((iocfg)->delay_per_opa_tap_hi << 8))
+
#define DELTA_D 1
/*
@@ -1623,7 +1626,7 @@ static int sdr_find_phase(struct socfpga_sdrseq *seq, int working,
*p = 0;
ret = sdr_find_phase_delay(seq, working, 0, grp, work,
- seq->iocfg->delay_per_opa_tap, p);
+ delay_per_opa_tap(seq->iocfg), p);
if (!ret)
return 0;
@@ -1651,7 +1654,7 @@ static int sdr_find_phase(struct socfpga_sdrseq *seq, int working,
static int sdr_working_phase(struct socfpga_sdrseq *seq, const u32 grp,
u32 *work_bgn, u32 *d, u32 *p, u32 *i)
{
- const u32 dtaps_per_ptap = seq->iocfg->delay_per_opa_tap /
+ const u32 dtaps_per_ptap = delay_per_opa_tap(seq->iocfg) /
seq->iocfg->delay_per_dqs_en_dchain_tap;
int ret;
@@ -1693,7 +1696,7 @@ static void sdr_backup_phase(struct socfpga_sdrseq *seq, const u32 grp,
} else {
(*p)--;
}
- tmp_delay = *work_bgn - seq->iocfg->delay_per_opa_tap;
+ tmp_delay = *work_bgn - delay_per_opa_tap(seq->iocfg);
scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *p);
for (d = 0; d <= seq->iocfg->dqs_en_delay_max && tmp_delay < *work_bgn;
@@ -1735,7 +1738,7 @@ static int sdr_nonworking_phase(struct socfpga_sdrseq *seq,
int ret;
(*p)++;
- *work_end += seq->iocfg->delay_per_opa_tap;
+ *work_end += delay_per_opa_tap(seq->iocfg);
if (*p > seq->iocfg->dqs_en_phase_max) {
/* Fiddle with FIFO. */
*p = 0;
@@ -1774,19 +1777,19 @@ static int sdr_find_window_center(struct socfpga_sdrseq *seq,
work_bgn, work_end, work_mid);
/* Get the middle delay to be less than a VFIFO delay */
tmp_delay = (seq->iocfg->dqs_en_phase_max + 1)
- * seq->iocfg->delay_per_opa_tap;
+ * delay_per_opa_tap(seq->iocfg);
debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay);
work_mid %= tmp_delay;
debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid);
- tmp_delay = rounddown(work_mid, seq->iocfg->delay_per_opa_tap);
+ tmp_delay = rounddown(work_mid, delay_per_opa_tap(seq->iocfg));
if (tmp_delay > seq->iocfg->dqs_en_phase_max
- * seq->iocfg->delay_per_opa_tap) {
+ * delay_per_opa_tap(seq->iocfg)) {
tmp_delay = seq->iocfg->dqs_en_phase_max
- * seq->iocfg->delay_per_opa_tap;
+ * delay_per_opa_tap(seq->iocfg);
}
- p = tmp_delay / seq->iocfg->delay_per_opa_tap;
+ p = tmp_delay / delay_per_opa_tap(seq->iocfg);
debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
@@ -1850,7 +1853,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdrseq *seq,
scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, 0);
/* Step 0: Determine number of delay taps for each phase tap. */
- dtaps_per_ptap = seq->iocfg->delay_per_opa_tap /
+ dtaps_per_ptap = delay_per_opa_tap(seq->iocfg) /
seq->iocfg->delay_per_dqs_en_dchain_tap;
/* Step 1: First push vfifo until we get a failing read. */
@@ -1894,7 +1897,7 @@ rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdrseq *seq,
p = p - 1;
}
- work_end -= seq->iocfg->delay_per_opa_tap;
+ work_end -= delay_per_opa_tap(seq->iocfg);
scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
d = 0;
@@ -2747,7 +2750,7 @@ static int rw_mgr_mem_calibrate_vfifo(struct socfpga_sdrseq *seq,
failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
/* USER Determine number of delay taps for each phase tap. */
- dtaps_per_ptap = DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap,
+ dtaps_per_ptap = DIV_ROUND_UP(delay_per_opa_tap(seq->iocfg),
seq->iocfg->delay_per_dqs_en_dchain_tap)
- 1;
@@ -3677,8 +3680,12 @@ static void hc_initialize_rom_data(void)
static void initialize_reg_file(struct socfpga_sdrseq *seq)
{
/* Initialize the register file with the correct data */
- writel(seq->misccfg->reg_file_init_seq_signature,
- &sdr_reg_file->signature);
+ u32 reg_file_init_seq_signature =
+ seq->misccfg->reg_file_init_seq_signature_ll |
+ (seq->misccfg->reg_file_init_seq_signature_lh << 8) |
+ (seq->misccfg->reg_file_init_seq_signature_hl << 16) |
+ (seq->misccfg->reg_file_init_seq_signature_hh << 24);
+ writel(reg_file_init_seq_signature, &sdr_reg_file->signature);
writel(0, &sdr_reg_file->debug_data_addr);
writel(0, &sdr_reg_file->cur_stage);
writel(0, &sdr_reg_file->fom);
@@ -3749,7 +3756,7 @@ static void initialize_tracking(struct socfpga_sdrseq *seq)
* Compute usable version of value in case we skip full
* computation later.
*/
- writel(DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap,
+ writel(DIV_ROUND_UP(delay_per_opa_tap(seq->iocfg),
seq->iocfg->delay_per_dchain_tap) - 1,
&sdr_reg_file->dtaps_per_ptap);
@@ -3834,7 +3841,7 @@ int sdram_calibration_full(struct socfpga_sdr *sdr)
seq.rwcfg->mem_if_read_dqs_width,
seq.rwcfg->mem_if_write_dqs_width,
seq.rwcfg->mem_data_width, seq.rwcfg->mem_data_mask_width,
- seq.iocfg->delay_per_opa_tap,
+ delay_per_opa_tap(seq.iocfg),
seq.iocfg->delay_per_dchain_tap);
debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
seq.iocfg->delay_per_dqs_en_dchain_tap,
--
2.20.1
next prev parent reply other threads:[~2019-10-15 20:10 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-15 20:10 [U-Boot] [RFC PATCH v2 00/18] arm: socfpga: gen5: move to DM Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 01/18] ddr: socfpga: gen5: constify altera_gen5_sdram_ops Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 02/18] dts: arm: socfpga: add label for clkmgr Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 03/18] arm: socfpga: gen5: increase SPL_SYS_MALLOC_F_LEN Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 04/18] timer: dw-apb: add reset handling Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 05/18] arm: socfpga: gen5: move initial reset handling to reset driver Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 06/18] arm: dts: socfpga: add settings for gen5 clk driver Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 07/18] arm: dts: socfpga: make clock nodes available in SPL Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 08/18] socfpga: gen5: add new tool to create handoff dtsi files Simon Goldschmidt
2019-10-22 17:10 ` Dalon L Westergreen
2019-10-22 17:13 ` Simon Goldschmidt
2019-10-23 16:03 ` Dalon L Westergreen
2019-10-23 19:22 ` Simon Goldschmidt
2019-10-24 14:25 ` Dalon L Westergreen
2019-10-24 14:29 ` Simon Goldschmidt
2019-10-24 17:29 ` Dalon L Westergreen
2019-10-24 18:00 ` Simon Goldschmidt
2019-10-15 20:10 ` Simon Goldschmidt [this message]
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 10/18] ddr: socfpga: gen5: fetch handoff information from 'of_to_platdata' Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 11/18] ddr: socfpga: gen5: read handoff information from devicetree Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 12/18] arm: socfpga: gen5: add readonly clk driver Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 13/18] arm: socfpga: gen5: enable DM CLK Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 14/18] arm: socfpga: gen5: move clock initialization to CLK driver Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 15/18] arm: socfpga: gen5: load CLK config from devicetree Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 16/18] spi: cadence_qspi: support DM_CLK Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 17/18] arm: socfpga: gen5: parse qspi clock from devictree Simon Goldschmidt
2019-10-15 20:10 ` [U-Boot] [RFC PATCH v2 18/18] socfpga: gen5: move CLK and SDRAM to DM Simon Goldschmidt
2019-10-23 20:36 ` [U-Boot] [RFC PATCH v2 00/18] arm: socfpga: gen5: move " Simon Goldschmidt
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