From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Goldschmidt Date: Tue, 15 Oct 2019 22:10:28 +0200 Subject: [U-Boot] [RFC PATCH v2 15/18] arm: socfpga: gen5: load CLK config from devicetree In-Reply-To: <20191015201032.20156-1-simon.k.r.goldschmidt@gmail.com> References: <20191015201032.20156-1-simon.k.r.goldschmidt@gmail.com> Message-ID: <20191015201032.20156-16-simon.k.r.goldschmidt@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Instead of using ad-hoc code in arch/arm, load clock config from devicetree. Signed-off-by: Simon Goldschmidt --- Changes in v2: None drivers/clk/altera/clk-gen5.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/clk/altera/clk-gen5.c b/drivers/clk/altera/clk-gen5.c index e8f435a798..a5425b7424 100644 --- a/drivers/clk/altera/clk-gen5.c +++ b/drivers/clk/altera/clk-gen5.c @@ -136,7 +136,13 @@ static int socfpga_gen5_clk_init(struct udevice *dev) struct socfpga_gen5_clk_platdata *plat = dev_get_platdata(dev); const struct socfpga_clock_manager *clock_manager_base = (const struct socfpga_clock_manager *)plat->regs; - const struct cm_config *cfg = cm_get_default_config(); + const struct cm_config *cfg = (const struct cm_config *) + dev_read_u8_array_ptr(dev, "altr,clk-mgr-cfg", sizeof(*cfg)); + + if (!cfg) { + dev_dbg(dev, "Failed to load CLK config\n"); + return -EINVAL; + } /* Start by being paranoid and gate all sw managed clocks */ -- 2.20.1