From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Goldschmidt Date: Tue, 15 Oct 2019 22:10:20 +0200 Subject: [U-Boot] [RFC PATCH v2 07/18] arm: dts: socfpga: make clock nodes available in SPL In-Reply-To: <20191015201032.20156-1-simon.k.r.goldschmidt@gmail.com> References: <20191015201032.20156-1-simon.k.r.goldschmidt@gmail.com> Message-ID: <20191015201032.20156-8-simon.k.r.goldschmidt@gmail.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de The socfpga gen5 clock driver will need some of the clock nodes to be preserved in the SPL devicetree. Mark them appropriately. Signed-off-by: Simon Goldschmidt --- Changes in v2: - split this patch from v1 5/6 arch/arm/dts/socfpga-common-u-boot.dtsi | 70 +++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/dts/socfpga-common-u-boot.dtsi b/arch/arm/dts/socfpga-common-u-boot.dtsi index aebe476e3f..7bc3b0021f 100644 --- a/arch/arm/dts/socfpga-common-u-boot.dtsi +++ b/arch/arm/dts/socfpga-common-u-boot.dtsi @@ -7,6 +7,12 @@ /{ soc { u-boot,dm-pre-reloc; + clkmgr at ffd04000 { + u-boot,dm-pre-reloc; + clocks { + u-boot,dm-pre-reloc; + }; + }; }; }; @@ -18,3 +24,67 @@ &sdr { u-boot,dm-pre-reloc; }; + +&osc1 { + u-boot,dm-pre-reloc; +}; + +&osc2 { + u-boot,dm-pre-reloc; +}; + +&f2s_periph_ref_clk { + u-boot,dm-pre-reloc; +}; + +&main_pll { + u-boot,dm-pre-reloc; +}; + +&mainclk { + u-boot,dm-pre-reloc; +}; + +&main_qspi_clk { + u-boot,dm-pre-reloc; +}; + +&main_nand_sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&periph_pll { + u-boot,dm-pre-reloc; +}; + +&per_qspi_clk { + u-boot,dm-pre-reloc; +}; + +&per_nand_mmc_clk { + u-boot,dm-pre-reloc; +}; + +&per_base_clk { + u-boot,dm-pre-reloc; +}; + +&l4_mp_clk { + u-boot,dm-pre-reloc; +}; + +&l4_sp_clk { + u-boot,dm-pre-reloc; +}; + +&sdmmc_clk { + u-boot,dm-pre-reloc; +}; + +&sdmmc_clk_divided { + u-boot,dm-pre-reloc; +}; + +&qspi_clk { + u-boot,dm-pre-reloc; +}; -- 2.20.1