From mboxrd@z Thu Jan 1 00:00:00 1970 From: lee.jones@linaro.org (Lee Jones) Date: Wed, 16 Oct 2019 11:04:38 +0100 Subject: [PATCH v3] mfd: mt6360: add pmic mt6360 driver In-Reply-To: References: <1569338741-2784-1-git-send-email-gene.chen.richtek@gmail.com> <20191004133324.GE18429@dell> List-Id: linux-mediatek@lists.infradead.org Message-ID: <20191016100438.GF4365@dell> To: linux-mediatek@lists.infradead.org On Tue, 15 Oct 2019, Gene Chen wrote: > Hi Lee, > > we find OF_MFD_CELL is not defined in mfd/core.h, which is ready to > merge to next kernel version > https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next-history/+/master/Next/merge.log It's here: Merging mfd/for-mfd-next (38a6fc63a3ea mfd: db8500-prcmu: Example using new OF_MFD_CELL/MFD_CELL_BASIC MACROs) $ git merge mfd/for-mfd-next Merge made by the 'recursive' strategy. drivers/mfd/ab8500-core.c | 138 +++++++++++++------------------------------ drivers/mfd/db8500-prcmu.c | 21 +++---- drivers/mfd/intel-lpss-pci.c | 28 ++++++--- drivers/mfd/ipaq-micro.c | 6 +- drivers/mfd/rk808.c | 22 ++----- include/linux/mfd/core.h | 29 +++++++++ <===== [THIS ONE] include/linux/mfd/rk808.h | 2 +- 7 files changed, 105 insertions(+), 141 deletions(-) https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next-history/+/master/Next/merge.log#4470 > may i ask how can i upstream without this definition? > e.g. we pull this patch and build pass, new patch without add macro define > > 2019-10-08 2:24 GMT+08:00, Gene Chen : > > Hi Jones, > > > > Thanks for review, we will fix some comment which your suggestion in next > > patch > > > > Lee Jones ? 2019?10?4? ?? ??9:33??? > >> > >> Wolfram, > >> > >> Would you be kind enough to grep for your name below? > >> > >> On Tue, 24 Sep 2019, Gene Chen wrote: > >> > >> > From: Gene Chen > >> > > >> > Add mfd driver for mt6360 pmic chip include > >> > Battery Charger/USB_PD/Flash LED/RGB LED/LDO/Buck > >> > > >> > Signed-off-by: Gene Chen >> > --- > >> > drivers/mfd/Kconfig | 12 + > >> > drivers/mfd/Makefile | 1 + > >> > drivers/mfd/mt6360-core.c | 463 > >> > +++++++++++++++++++++++++++++++++++++ > >> > include/linux/mfd/mt6360-private.h | 279 ++++++++++++++++++++++ > >> > include/linux/mfd/mt6360.h | 33 +++ > >> > 5 files changed, 788 insertions(+) > >> > create mode 100644 drivers/mfd/mt6360-core.c > >> > create mode 100644 include/linux/mfd/mt6360-private.h > >> > create mode 100644 include/linux/mfd/mt6360.h > >> > > >> > changelogs between v1 & v2 > >> > - include missing header file > >> > > >> > changelogs between v2 & v3 > >> > - add changelogs > >> > > >> > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > >> > index f129f96..a422c76 100644 > >> > --- a/drivers/mfd/Kconfig > >> > +++ b/drivers/mfd/Kconfig > >> > @@ -862,6 +862,18 @@ config MFD_MAX8998 > >> > additional drivers must be enabled in order to use the > >> > functionality > >> > of the device. > >> > > >> > +config MFD_MT6360 > >> > + tristate "Mediatek MT6360 SubPMIC" > >> > + select MFD_CORE > >> > + select REGMAP_I2C > >> > + select REGMAP_IRQ > >> > + depends on I2C > >> > + help > >> > + Say Y here to enable MT6360 PMU/PMIC/LDO functional support. > >> > + PMU part include charger, flashlight, rgb led > >> > + PMIC part include 2-channel BUCKs and 2-channel LDOs > >> > + LDO part include 4-channel LDOs > >> > >> PMU part includes Charger, Flashlight, RGB and LED > >> PMIC part includes 2-channel BUCKs and 2-channel LDOs > >> LDO part includes 4-channel LDOs > >> > > > > ACK. RGB LED is one of indicator light, only single feature > > > >> > config MFD_MT6397 > >> > tristate "MediaTek MT6397 PMIC Support" > >> > select MFD_CORE > >> > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > >> > index f026ada..77a8f0b 100644 > >> > --- a/drivers/mfd/Makefile > >> > +++ b/drivers/mfd/Makefile > >> > @@ -241,6 +241,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += > >> > intel-soc-pmic.o > >> > obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o > >> > obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o > >> > obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += > >> > intel_soc_pmic_chtdc_ti.o > >> > +obj-$(CONFIG_MFD_MT6360) += mt6360-core.o > >> > obj-$(CONFIG_MFD_MT6397) += mt6397-core.o > >> > > >> > obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o > >> > diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c > >> > new file mode 100644 > >> > index 0000000..d3580618 > >> > --- /dev/null > >> > +++ b/drivers/mfd/mt6360-core.c > >> > @@ -0,0 +1,463 @@ > >> > +// SPDX-License-Identifier: GPL-2.0 > >> > +/* > >> > + * Copyright (c) 2019 MediaTek Inc. > >> > + */ > >> > + > >> > +#include > >> > +#include > >> > +#include > >> > +#include > >> > +#include > >> > +#include > >> > +#include > >> > +#include > >> > + > >> > +#include > >> > +#include > >> > + > >> > +/* reg 0 -> 0 ~ 7 */ > >> > +#define MT6360_CHG_TREG_EVT (4) > >> > +#define MT6360_CHG_AICR_EVT (5) > >> > +#define MT6360_CHG_MIVR_EVT (6) > >> > +#define MT6360_PWR_RDY_EVT (7) > >> > +/* REG 1 -> 8 ~ 15 */ > >> > +#define MT6360_CHG_BATSYSUV_EVT (9) > >> > +#define MT6360_FLED_CHG_VINOVP_EVT (11) > >> > +#define MT6360_CHG_VSYSUV_EVT (12) > >> > +#define MT6360_CHG_VSYSOV_EVT (13) > >> > +#define MT6360_CHG_VBATOV_EVT (14) > >> > +#define MT6360_CHG_VBUSOV_EVT (15) > >> > +/* REG 2 -> 16 ~ 23 */ > >> > +/* REG 3 -> 24 ~ 31 */ > >> > +#define MT6360_WD_PMU_DET (25) > >> > +#define MT6360_WD_PMU_DONE (26) > >> > +#define MT6360_CHG_TMRI (27) > >> > +#define MT6360_CHG_ADPBADI (29) > >> > +#define MT6360_CHG_RVPI (30) > >> > +#define MT6360_OTPI (31) > >> > +/* REG 4 -> 32 ~ 39 */ > >> > +#define MT6360_CHG_AICCMEASL (32) > >> > +#define MT6360_CHGDET_DONEI (34) > >> > +#define MT6360_WDTMRI (35) > >> > +#define MT6360_SSFINISHI (36) > >> > +#define MT6360_CHG_RECHGI (37) > >> > +#define MT6360_CHG_TERMI (38) > >> > +#define MT6360_CHG_IEOCI (39) > >> > +/* REG 5 -> 40 ~ 47 */ > >> > +#define MT6360_PUMPX_DONEI (40) > >> > +#define MT6360_BAT_OVP_ADC_EVT (41) > >> > +#define MT6360_TYPEC_OTP_EVT (42) > >> > +#define MT6360_ADC_WAKEUP_EVT (43) > >> > +#define MT6360_ADC_DONEI (44) > >> > +#define MT6360_BST_BATUVI (45) > >> > +#define MT6360_BST_VBUSOVI (46) > >> > +#define MT6360_BST_OLPI (47) > >> > +/* REG 6 -> 48 ~ 55 */ > >> > +#define MT6360_ATTACH_I (48) > >> > +#define MT6360_DETACH_I (49) > >> > +#define MT6360_QC30_STPDONE (51) > >> > +#define MT6360_QC_VBUSDET_DONE (52) > >> > +#define MT6360_HVDCP_DET (53) > >> > +#define MT6360_CHGDETI (54) > >> > +#define MT6360_DCDTI (55) > >> > +/* REG 7 -> 56 ~ 63 */ > >> > +#define MT6360_FOD_DONE_EVT (56) > >> > +#define MT6360_FOD_OV_EVT (57) > >> > +#define MT6360_CHRDET_UVP_EVT (58) > >> > +#define MT6360_CHRDET_OVP_EVT (59) > >> > +#define MT6360_CHRDET_EXT_EVT (60) > >> > +#define MT6360_FOD_LR_EVT (61) > >> > +#define MT6360_FOD_HR_EVT (62) > >> > +#define MT6360_FOD_DISCHG_FAIL_EVT (63) > >> > +/* REG 8 -> 64 ~ 71 */ > >> > +#define MT6360_USBID_EVT (64) > >> > +#define MT6360_APWDTRST_EVT (65) > >> > +#define MT6360_EN_EVT (66) > >> > +#define MT6360_QONB_RST_EVT (67) > >> > +#define MT6360_MRSTB_EVT (68) > >> > +#define MT6360_OTP_EVT (69) > >> > +#define MT6360_VDDAOV_EVT (70) > >> > +#define MT6360_SYSUV_EVT (71) > >> > +/* REG 9 -> 72 ~ 79 */ > >> > +#define MT6360_FLED_STRBPIN_EVT (72) > >> > +#define MT6360_FLED_TORPIN_EVT (73) > >> > +#define MT6360_FLED_TX_EVT (74) > >> > +#define MT6360_FLED_LVF_EVT (75) > >> > +#define MT6360_FLED2_SHORT_EVT (78) > >> > +#define MT6360_FLED1_SHORT_EVT (79) > >> > +/* REG 10 -> 80 ~ 87 */ > >> > +#define MT6360_FLED2_STRB_EVT (80) > >> > +#define MT6360_FLED1_STRB_EVT (81) > >> > +#define MT6360_FLED2_STRB_TO_EVT (82) > >> > +#define MT6360_FLED1_STRB_TO_EVT (83) > >> > +#define MT6360_FLED2_TOR_EVT (84) > >> > +#define MT6360_FLED1_TOR_EVT (85) > >> > +/* REG 11 -> 88 ~ 95 */ > >> > +/* REG 12 -> 96 ~ 103 */ > >> > +#define MT6360_BUCK1_PGB_EVT (96) > >> > +#define MT6360_BUCK1_OC_EVT (100) > >> > +#define MT6360_BUCK1_OV_EVT (101) > >> > +#define MT6360_BUCK1_UV_EVT (102) > >> > +/* REG 13 -> 104 ~ 111 */ > >> > +#define MT6360_BUCK2_PGB_EVT (104) > >> > +#define MT6360_BUCK2_OC_EVT (108) > >> > +#define MT6360_BUCK2_OV_EVT (109) > >> > +#define MT6360_BUCK2_UV_EVT (110) > >> > +/* REG 14 -> 112 ~ 119 */ > >> > +#define MT6360_LDO1_OC_EVT (113) > >> > +#define MT6360_LDO2_OC_EVT (114) > >> > +#define MT6360_LDO3_OC_EVT (115) > >> > +#define MT6360_LDO5_OC_EVT (117) > >> > +#define MT6360_LDO6_OC_EVT (118) > >> > +#define MT6360_LDO7_OC_EVT (119) > >> > +/* REG 15 -> 120 ~ 127 */ > >> > +#define MT6360_LDO1_PGB_EVT (121) > >> > +#define MT6360_LDO2_PGB_EVT (122) > >> > +#define MT6360_LDO3_PGB_EVT (123) > >> > +#define MT6360_LDO5_PGB_EVT (125) > >> > +#define MT6360_LDO6_PGB_EVT (126) > >> > +#define MT6360_LDO7_PGB_EVT (127) > >> > + > >> > +#define MT6360_REGMAP_IRQ_REG(_irq_evt) \ > >> > + REGMAP_IRQ_REG(_irq_evt, (_irq_evt) / 8, BIT((_irq_evt) % 8)) > >> > + > >> > +#define MT6360_MFD_CELL(_name) \ > >> > + { \ > >> > + .name = #_name, \ > >> > + .of_compatible = "mediatek," #_name, \ > >> > + .num_resources = ARRAY_SIZE(_name##_resources), \ > >> > + .resources = _name##_resources, \ > >> > + } > >> > >> Please do not roll your own MACROS like this. If they are helpful for > >> you, they are likely to be helpful for others. However, this is your > >> lucky day, as we've been here before. Please rebase onto the MFD tree > >> where you will find some pre-authored macros which aren't too > >> dissimilar to this one. Please use one of those instead. > >> > > > > ACK > > > >> > +static const struct regmap_irq mt6360_pmu_irqs[] = { > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_TREG_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_AICR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_MIVR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_PWR_RDY_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_BATSYSUV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED_CHG_VINOVP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_VSYSUV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_VSYSOV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_VBATOV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_VBUSOV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_WD_PMU_DET), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_WD_PMU_DONE), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_TMRI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_ADPBADI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_RVPI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_OTPI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_AICCMEASL), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHGDET_DONEI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_WDTMRI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_SSFINISHI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_RECHGI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_TERMI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_IEOCI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_PUMPX_DONEI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_TREG_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BAT_OVP_ADC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_TYPEC_OTP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_ADC_WAKEUP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_ADC_DONEI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BST_BATUVI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BST_VBUSOVI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BST_OLPI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_ATTACH_I), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_DETACH_I), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_QC30_STPDONE), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_QC_VBUSDET_DONE), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_HVDCP_DET), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHGDETI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_DCDTI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FOD_DONE_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FOD_OV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHRDET_UVP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHRDET_OVP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHRDET_EXT_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FOD_LR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FOD_HR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FOD_DISCHG_FAIL_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_USBID_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_APWDTRST_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_EN_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_QONB_RST_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_MRSTB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_OTP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_VDDAOV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_SYSUV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED_STRBPIN_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED_TORPIN_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED_TX_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED_LVF_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED2_SHORT_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED1_SHORT_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED2_STRB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED1_STRB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED2_STRB_TO_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED1_STRB_TO_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED2_TOR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED1_TOR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK1_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK1_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK1_OV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK1_UV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK2_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK2_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK2_OV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK2_UV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO1_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO2_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO3_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO5_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO6_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO7_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO1_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO2_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO3_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO5_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO6_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO7_PGB_EVT), > >> > +}; > >> > + > >> > +static int mt6360_pmu_handle_post_irq(void *irq_drv_data) > >> > +{ > >> > + struct mt6360_pmu_info *mpi = irq_drv_data; > >> > + > >> > + return regmap_update_bits(mpi->regmap, > >> > + MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG, > >> > MT6360_IRQ_RETRIG); > >> > +} > >> > + > >> > +static const struct regmap_irq_chip mt6360_pmu_irq_chip = { > >> > + .irqs = mt6360_pmu_irqs, > >> > + .num_irqs = ARRAY_SIZE(mt6360_pmu_irqs), > >> > + .num_regs = MT6360_PMU_IRQ_REGNUM, > >> > + .mask_base = MT6360_PMU_CHG_MASK1, > >> > + .status_base = MT6360_PMU_CHG_IRQ1, > >> > + .ack_base = MT6360_PMU_CHG_IRQ1, > >> > + .init_ack_masked = true, > >> > + .use_ack = true, > >> > + .handle_post_irq = mt6360_pmu_handle_post_irq, > >> > +}; > >> > + > >> > +static const struct regmap_config mt6360_pmu_regmap_config = { > >> > + .reg_bits = 8, > >> > + .val_bits = 8, > >> > + .max_register = MT6360_PMU_MAXREG, > >> > +}; > >> > + > >> > +static const struct resource mt6360_adc_resources[] = { > >> > + DEFINE_RES_IRQ_NAMED(MT6360_ADC_DONEI, "adc_donei"), > >> > +}; > >> > + > >> > +static const struct resource mt6360_chg_resources[] = { > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_TREG_EVT, "chg_treg_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_PWR_RDY_EVT, "pwr_rdy_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_BATSYSUV_EVT, > >> > "chg_batsysuv_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSUV_EVT, "chg_vsysuv_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSOV_EVT, "chg_vsysov_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBATOV_EVT, "chg_vbatov_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBUSOV_EVT, "chg_vbusov_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_AICCMEASL, "chg_aiccmeasl"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_WDTMRI, "wdtmri"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_RECHGI, "chg_rechgi"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_TERMI, "chg_termi"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_IEOCI, "chg_ieoci"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_PUMPX_DONEI, "pumpx_donei"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_ATTACH_I, "attach_i"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHRDET_EXT_EVT, "chrdet_ext_evt"), > >> > +}; > >> > + > >> > +static const struct resource mt6360_led_resources[] = { > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED_CHG_VINOVP_EVT, > >> > "fled_chg_vinovp_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED_LVF_EVT, "fled_lvf_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED2_SHORT_EVT, "fled2_short_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED1_SHORT_EVT, "fled1_short_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED2_STRB_TO_EVT, > >> > "fled2_strb_to_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, > >> > "fled1_strb_to_evt"), > >> > +}; > >> > + > >> > +static const struct resource mt6360_pmic_resources[] = { > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_UV_EVT, "buck1_uv_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_PGB_EVT, "buck2_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OC_EVT, "buck2_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OV_EVT, "buck2_ov_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_UV_EVT, "buck2_uv_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"), > >> > +}; > >> > + > >> > +static const struct resource mt6360_ldo_resources[] = { > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO5_OC_EVT, "ldo5_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO1_PGB_EVT, "ldo1_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO2_PGB_EVT, "ldo2_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO3_PGB_EVT, "ldo3_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO5_PGB_EVT, "ldo5_pgb_evt"), > >> > +}; > >> > + > >> > +static const struct mfd_cell mt6360_devs[] = { > >> > + MT6360_MFD_CELL(mt6360_adc), > >> > + MT6360_MFD_CELL(mt6360_chg), > >> > + MT6360_MFD_CELL(mt6360_led), > >> > + MT6360_MFD_CELL(mt6360_pmic), > >> > + MT6360_MFD_CELL(mt6360_ldo), > >> > + /* tcpc dev */ > >> > + { > >> > + .name = "mt6360_tcpc", > >> > + .of_compatible = "mediatek,mt6360_tcpc", > >> > >> There is a macro for this too (OF_MFD_CELL()) > >> > > > > ACK > > > >> > + }, > >> > +}; > >> > + > >> > +static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { > >> > + MT6360_PMU_SLAVEID, > >> > + MT6360_PMIC_SLAVEID, > >> > + MT6360_LDO_SLAVEID, > >> > + MT6360_TCPC_SLAVEID, > >> > +}; > >> > + > >> > +static int mt6360_pmu_probe(struct i2c_client *client, > >> > + const struct i2c_device_id *id) > >> > >> If you use .probe_new (see below) you can omit the 'id' param. > >> > > > > ACK > > > >> > +{ > >> > + struct mt6360_pmu_info *mpi; > >> > >> We normally call this ddata. > >> > > > > ACK > > > >> > + unsigned int reg_data = 0; > >> > + int i, ret; > >> > + > >> > + mpi = devm_kzalloc(&client->dev, sizeof(*mpi), GFP_KERNEL); > >> > + if (!mpi) > >> > + return -ENOMEM; > >> > >> '\n' here. > >> > > > > ACK > > > >> > + mpi->dev = &client->dev; > >> > + i2c_set_clientdata(client, mpi); > >> > + > >> > + /* regmap regiser */ > >> > >> This comment is spelt incorrectly and doesn't really add anything. > >> > > > > ACK > > > >> > + mpi->regmap = devm_regmap_init_i2c(client, > >> > &mt6360_pmu_regmap_config); > >> > + if (IS_ERR(mpi->regmap)) { > >> > + dev_err(&client->dev, "regmap register fail\n"); > >> > >> "Failed to register regmap" > >> > > > > ACK > > > >> > + return PTR_ERR(mpi->regmap); > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + /* chip id check */ > >> > >> Again, the code is pretty obvious. > >> > > > > ACK > > > >> > + ret = regmap_read(mpi->regmap, MT6360_PMU_DEV_INFO, ®_data); > >> > + if (ret < 0) { > >> > + dev_err(&client->dev, "device not found\n"); > >> > >> "Device not found" > >> > > > > ACK > > > >> > + return ret; > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + if ((reg_data & CHIP_VEN_MASK) != CHIP_VEN_MT6360) { > >> > + dev_err(&client->dev, "not mt6360 chip\n"); > >> > >> "Device not supported" > >> > > > > ACK > > > >> > + return -ENODEV; > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + mpi->chip_rev = reg_data & CHIP_REV_MASK; > >> > >> Do this above the check, then do > >> > >> (mpi->chip_rev != CHIP_VEN_MT6360) > >> > >> ... above. > >> > > > > ACK > > > >> > + /* irq register */ > >> > >> Please remove all of these comments. > >> > > > > ACK > > > >> > + memcpy(&mpi->irq_chip, &mt6360_pmu_irq_chip, > >> > sizeof(mpi->irq_chip)); > >> > >> Why do we need to make a copy of it? > >> > > > > consider of using mutiple mt6360 chips, we can seperate diff i2c > > irq_chip.name by device_name originally > > but we can't find silimar case by overview other mfd driver > > we will delete this > > > >> > + mpi->irq_chip.name = dev_name(&client->dev); > >> > >> We already know the name. Why do we need to do this dynamically? > >> > > > > same as above > > > >> > + mpi->irq_chip.irq_drv_data = mpi; > >> > >> We already saved ddata. Why do we need to save it here as well? > >> > > > > we implement ops ".handle_post_irq" for irq retrigger when irq stuck keep > > low > > > >> > + ret = devm_regmap_add_irq_chip(&client->dev, mpi->regmap, > >> > client->irq, > >> > + IRQF_TRIGGER_FALLING, 0, > >> > &mpi->irq_chip, > >> > + &mpi->irq_data); > >> > + if (ret < 0) { > >> > >> Is (ret > 0) valid? > >> > > > > we consider mt6360 driver need add irq_chip for full functionality > > > >> > + dev_err(&client->dev, "regmap irq chip add fail\n"); > >> > >> "Failed to add Regmap IRQ Chip" > >> > > > > ACK > > > >> > + return ret; > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + /* new i2c slave device */ > >> > + for (i = 0; i < MT6360_SLAVE_MAX; i++) { > >> > + if (mt6360_slave_addr[i] == client->addr) { > >> > + mpi->i2c[i] = client; > >> > + continue; > >> > + } > >> > + mpi->i2c[i] = i2c_new_dummy(client->adapter, > >> > + mt6360_slave_addr[i]); > >> > + if (!mpi->i2c[i]) { > >> > + dev_err(&client->dev, "new i2c dev [%d] fail\n", > >> > i); > >> > + ret = -ENODEV; > >> > + goto out; > >> > + } > >> > + i2c_set_clientdata(mpi->i2c[i], mpi); > >> > + } > >> > >> This doesn't look right to me. > >> > >> Wolfram, would you be kind enough to take a look? > >> > >> '\n' here. > >> > > > > ACK > > > >> > + /* mfd cell register */ > >> > + ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, > >> > + mt6360_devs, ARRAY_SIZE(mt6360_devs), > >> > NULL, > >> > + 0, > >> > regmap_irq_get_domain(mpi->irq_data)); > >> > + if (ret < 0) { > >> > + dev_err(&client->dev, "mfd add cells fail\n"); > >> > + goto out; > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + dev_info(&client->dev, "Successfully probed\n"); > >> > >> Please remove this line. It doesn't provide anything. > >> > > > > ACK > > > >> > + return 0; > >> > +out: > >> > + while (--i >= 0) { > >> > + if (mpi->i2c[i]->addr == client->addr) > >> > + continue; > >> > + i2c_unregister_device(mpi->i2c[i]); > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + return ret; > >> > +} > >> > + > >> > +static int mt6360_pmu_remove(struct i2c_client *client) > >> > +{ > >> > + struct mt6360_pmu_info *mpi = i2c_get_clientdata(client); > >> > + int i; > >> > + > >> > + for (i = 0; i < MT6360_SLAVE_MAX; i++) { > >> > + if (mpi->i2c[i]->addr == client->addr) > >> > + continue; > >> > + i2c_unregister_device(mpi->i2c[i]); > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + return 0; > >> > +} > >> > + > >> > +static int __maybe_unused mt6360_pmu_suspend(struct device *dev) > >> > +{ > >> > + struct i2c_client *i2c = to_i2c_client(dev); > >> > + > >> > + if (device_may_wakeup(dev)) > >> > + enable_irq_wake(i2c->irq); > >> > >> '\n' here. > >> > > > > ACK > > > >> > + return 0; > >> > +} > >> > + > >> > +static int __maybe_unused mt6360_pmu_resume(struct device *dev) > >> > +{ > >> > + > >> > + struct i2c_client *i2c = to_i2c_client(dev); > >> > + > >> > + if (device_may_wakeup(dev)) > >> > + disable_irq_wake(i2c->irq); > >> > >> '\n' here. > >> > > > > ACK > > > >> > + return 0; > >> > +} > >> > + > >> > +static SIMPLE_DEV_PM_OPS(mt6360_pmu_pm_ops, > >> > + mt6360_pmu_suspend, mt6360_pmu_resume); > >> > + > >> > +static const struct of_device_id __maybe_unused mt6360_pmu_of_id[] = { > >> > + { .compatible = "mediatek,mt6360_pmu", }, > >> > + {}, > >> > +}; > >> > +MODULE_DEVICE_TABLE(of, mt6360_pmu_of_id); > >> > + > >> > +static const struct i2c_device_id mt6360_pmu_id[] = { > >> > + { "mt6360_pmu", 0 }, > >> > + {}, > >> > +}; > >> > +MODULE_DEVICE_TABLE(i2c, mt6360_pmu_id); > >> > >> If you use .probe_new (see below, you can remove this table. > >> > > > > ACK > > > >> > +static struct i2c_driver mt6360_pmu_driver = { > >> > + .driver = { > >> > + .name = "mt6360_pmu", > >> > + .owner = THIS_MODULE, > >> > >> This is no longer required. > >> > > > > ACK > > > >> > + .pm = &mt6360_pmu_pm_ops, > >> > + .of_match_table = of_match_ptr(mt6360_pmu_of_id), > >> > + }, > >> > + .probe = mt6360_pmu_probe, > >> > >> Use .probe_new here. > >> > > > > ACK > > > >> > + .remove = mt6360_pmu_remove, > >> > + .id_table = mt6360_pmu_id, > >> > +}; > >> > +module_i2c_driver(mt6360_pmu_driver); > >> > + > >> > +MODULE_AUTHOR("CY_Huang "); > >> > +MODULE_DESCRIPTION("MT6360 PMU I2C Driver"); > >> > +MODULE_LICENSE("GPL"); > >> > +MODULE_VERSION("1.0.0"); > >> > diff --git a/include/linux/mfd/mt6360-private.h > >> > b/include/linux/mfd/mt6360-private.h > >> > new file mode 100644 > >> > index 0000000..b07b3d9 > >> > --- /dev/null > >> > +++ b/include/linux/mfd/mt6360-private.h > >> > >> Why do you need 2 header files? > >> > > > > According to our architecture as attachment, > > mt6360 have 4 i2c slave address for different parts > > so we set whole register table in mt6360-private.h, it will be > > included by other modules > > we will delete it next patch > > and we will add until we use it > > > >> > @@ -0,0 +1,279 @@ > >> > +/* SPDX-License-Identifier: GPL-2.0 */ > >> > +/* > >> > + * Copyright (c) 2019 MediaTek Inc. > >> > + */ > >> > + > >> > +#ifndef __MT6360_PRIVATE_H__ > >> > +#define __MT6360_PRIVATE_H__ > >> > >> __MFD_MT6360_H__ > >> > >> > +#include > >> > + > >> > +/* PMU register defininition */ > >> > +#define MT6360_PMU_DEV_INFO (0x00) > >> > +#define MT6360_PMU_CORE_CTRL1 (0x01) > >> > +#define MT6360_PMU_RST1 (0x02) > >> > +#define MT6360_PMU_CRCEN (0x03) > >> > +#define MT6360_PMU_RST_PAS_CODE1 (0x04) > >> > +#define MT6360_PMU_RST_PAS_CODE2 (0x05) > >> > +#define MT6360_PMU_CORE_CTRL2 (0x06) > >> > +#define MT6360_PMU_TM_PAS_CODE1 (0x07) > >> > +#define MT6360_PMU_TM_PAS_CODE2 (0x08) > >> > +#define MT6360_PMU_TM_PAS_CODE3 (0x09) > >> > +#define MT6360_PMU_TM_PAS_CODE4 (0x0A) > >> > +#define MT6360_PMU_IRQ_IND (0x0B) > >> > +#define MT6360_PMU_IRQ_MASK (0x0C) > >> > +#define MT6360_PMU_IRQ_SET (0x0D) > >> > +#define MT6360_PMU_SHDN_CTRL (0x0E) > >> > +#define MT6360_PMU_TM_INF (0x0F) > >> > +#define MT6360_PMU_I2C_CTRL (0x10) > >> > +#define MT6360_PMU_CHG_CTRL1 (0x11) > >> > +#define MT6360_PMU_CHG_CTRL2 (0x12) > >> > +#define MT6360_PMU_CHG_CTRL3 (0x13) > >> > +#define MT6360_PMU_CHG_CTRL4 (0x14) > >> > +#define MT6360_PMU_CHG_CTRL5 (0x15) > >> > +#define MT6360_PMU_CHG_CTRL6 (0x16) > >> > +#define MT6360_PMU_CHG_CTRL7 (0x17) > >> > +#define MT6360_PMU_CHG_CTRL8 (0x18) > >> > +#define MT6360_PMU_CHG_CTRL9 (0x19) > >> > +#define MT6360_PMU_CHG_CTRL10 (0x1A) > >> > +#define MT6360_PMU_CHG_CTRL11 (0x1B) > >> > +#define MT6360_PMU_CHG_CTRL12 (0x1C) > >> > +#define MT6360_PMU_CHG_CTRL13 (0x1D) > >> > +#define MT6360_PMU_CHG_CTRL14 (0x1E) > >> > +#define MT6360_PMU_CHG_CTRL15 (0x1F) > >> > +#define MT6360_PMU_CHG_CTRL16 (0x20) > >> > +#define MT6360_PMU_CHG_AICC_RESULT (0x21) > >> > +#define MT6360_PMU_DEVICE_TYPE (0x22) > >> > +#define MT6360_PMU_QC_CONTROL1 (0x23) > >> > +#define MT6360_PMU_QC_CONTROL2 (0x24) > >> > +#define MT6360_PMU_QC30_CONTROL1 (0x25) > >> > +#define MT6360_PMU_QC30_CONTROL2 (0x26) > >> > +#define MT6360_PMU_USB_STATUS1 (0x27) > >> > +#define MT6360_PMU_QC_STATUS1 (0x28) > >> > +#define MT6360_PMU_QC_STATUS2 (0x29) > >> > +#define MT6360_PMU_CHG_PUMP (0x2A) > >> > +#define MT6360_PMU_CHG_CTRL17 (0x2B) > >> > +#define MT6360_PMU_CHG_CTRL18 (0x2C) > >> > +#define MT6360_PMU_CHRDET_CTRL1 (0x2D) > >> > +#define MT6360_PMU_CHRDET_CTRL2 (0x2E) > >> > +#define MT6360_PMU_DPDN_CTRL (0x2F) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL1 (0x30) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL2 (0x31) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL3 (0x32) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL4 (0x33) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL5 (0x34) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL6 (0x35) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL7 (0x36) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL8 (0x37) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL9 (0x38) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL10 (0x39) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL11 (0x3A) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL12 (0x3B) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL13 (0x3C) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL14 (0x3D) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL15 (0x3E) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL16 (0x3F) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL17 (0x40) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL18 (0x41) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL19 (0x42) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL20 (0x43) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL21 (0x44) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL22 (0x45) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL23 (0x46) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL24 (0x47) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL25 (0x48) > >> > +#define MT6360_PMU_BC12_CTRL (0x49) > >> > +#define MT6360_PMU_CHG_STAT (0x4A) > >> > +#define MT6360_PMU_RESV1 (0x4B) > >> > +#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH (0x4E) > >> > +#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL (0x4F) > >> > +#define MT6360_PMU_TYPEC_OTP_HYST_TH (0x50) > >> > +#define MT6360_PMU_TYPEC_OTP_CTRL (0x51) > >> > +#define MT6360_PMU_ADC_BAT_DATA_H (0x52) > >> > +#define MT6360_PMU_ADC_BAT_DATA_L (0x53) > >> > +#define MT6360_PMU_IMID_BACKBST_ON (0x54) > >> > +#define MT6360_PMU_IMID_BACKBST_OFF (0x55) > >> > +#define MT6360_PMU_ADC_CONFIG (0x56) > >> > +#define MT6360_PMU_ADC_EN2 (0x57) > >> > +#define MT6360_PMU_ADC_IDLE_T (0x58) > >> > +#define MT6360_PMU_ADC_RPT_1 (0x5A) > >> > +#define MT6360_PMU_ADC_RPT_2 (0x5B) > >> > +#define MT6360_PMU_ADC_RPT_3 (0x5C) > >> > +#define MT6360_PMU_ADC_RPT_ORG1 (0x5D) > >> > +#define MT6360_PMU_ADC_RPT_ORG2 (0x5E) > >> > +#define MT6360_PMU_BAT_OVP_TH_SEL_CODEH (0x5F) > >> > +#define MT6360_PMU_BAT_OVP_TH_SEL_CODEL (0x60) > >> > +#define MT6360_PMU_CHG_CTRL19 (0x61) > >> > +#define MT6360_PMU_VDDASUPPLY (0x62) > >> > +#define MT6360_PMU_BC12_MANUAL (0x63) > >> > +#define MT6360_PMU_CHGDET_FUNC (0x64) > >> > +#define MT6360_PMU_FOD_CTRL (0x65) > >> > +#define MT6360_PMU_CHG_CTRL20 (0x66) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL26 (0x67) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL27 (0x68) > >> > +#define MT6360_PMU_RESV2 (0x69) > >> > +#define MT6360_PMU_USBID_CTRL1 (0x6D) > >> > +#define MT6360_PMU_USBID_CTRL2 (0x6E) > >> > +#define MT6360_PMU_USBID_CTRL3 (0x6F) > >> > +#define MT6360_PMU_FLED_CFG (0x70) > >> > +#define MT6360_PMU_RESV3 (0x71) > >> > +#define MT6360_PMU_FLED1_CTRL (0x72) > >> > +#define MT6360_PMU_FLED_STRB_CTRL (0x73) > >> > +#define MT6360_PMU_FLED1_STRB_CTRL2 (0x74) > >> > +#define MT6360_PMU_FLED1_TOR_CTRL (0x75) > >> > +#define MT6360_PMU_FLED2_CTRL (0x76) > >> > +#define MT6360_PMU_RESV4 (0x77) > >> > +#define MT6360_PMU_FLED2_STRB_CTRL2 (0x78) > >> > +#define MT6360_PMU_FLED2_TOR_CTRL (0x79) > >> > +#define MT6360_PMU_FLED_VMIDTRK_CTRL1 (0x7A) > >> > +#define MT6360_PMU_FLED_VMID_RTM (0x7B) > >> > +#define MT6360_PMU_FLED_VMIDTRK_CTRL2 (0x7C) > >> > +#define MT6360_PMU_FLED_PWSEL (0x7D) > >> > +#define MT6360_PMU_FLED_EN (0x7E) > >> > +#define MT6360_PMU_FLED_Hidden1 (0x7F) > >> > +#define MT6360_PMU_RGB_EN (0x80) > >> > +#define MT6360_PMU_RGB1_ISNK (0x81) > >> > +#define MT6360_PMU_RGB2_ISNK (0x82) > >> > +#define MT6360_PMU_RGB3_ISNK (0x83) > >> > +#define MT6360_PMU_RGB_ML_ISNK (0x84) > >> > +#define MT6360_PMU_RGB1_DIM (0x85) > >> > +#define MT6360_PMU_RGB2_DIM (0x86) > >> > +#define MT6360_PMU_RGB3_DIM (0x87) > >> > +#define MT6360_PMU_RESV5 (0x88) > >> > +#define MT6360_PMU_RGB12_Freq (0x89) > >> > +#define MT6360_PMU_RGB34_Freq (0x8A) > >> > +#define MT6360_PMU_RGB1_Tr (0x8B) > >> > +#define MT6360_PMU_RGB1_Tf (0x8C) > >> > +#define MT6360_PMU_RGB1_TON_TOFF (0x8D) > >> > +#define MT6360_PMU_RGB2_Tr (0x8E) > >> > +#define MT6360_PMU_RGB2_Tf (0x8F) > >> > +#define MT6360_PMU_RGB2_TON_TOFF (0x90) > >> > +#define MT6360_PMU_RGB3_Tr (0x91) > >> > +#define MT6360_PMU_RGB3_Tf (0x92) > >> > +#define MT6360_PMU_RGB3_TON_TOFF (0x93) > >> > +#define MT6360_PMU_RGB_Hidden_CTRL1 (0x94) > >> > +#define MT6360_PMU_RGB_Hidden_CTRL2 (0x95) > >> > +#define MT6360_PMU_RESV6 (0x97) > >> > +#define MT6360_PMU_SPARE1 (0x9A) > >> > +#define MT6360_PMU_SPARE2 (0xA0) > >> > +#define MT6360_PMU_SPARE3 (0xB0) > >> > +#define MT6360_PMU_SPARE4 (0xC0) > >> > +#define MT6360_PMU_CHG_IRQ1 (0xD0) > >> > +#define MT6360_PMU_CHG_IRQ2 (0xD1) > >> > +#define MT6360_PMU_CHG_IRQ3 (0xD2) > >> > +#define MT6360_PMU_CHG_IRQ4 (0xD3) > >> > +#define MT6360_PMU_CHG_IRQ5 (0xD4) > >> > +#define MT6360_PMU_CHG_IRQ6 (0xD5) > >> > +#define MT6360_PMU_QC_IRQ (0xD6) > >> > +#define MT6360_PMU_FOD_IRQ (0xD7) > >> > +#define MT6360_PMU_BASE_IRQ (0xD8) > >> > +#define MT6360_PMU_FLED_IRQ1 (0xD9) > >> > +#define MT6360_PMU_FLED_IRQ2 (0xDA) > >> > +#define MT6360_PMU_RGB_IRQ (0xDB) > >> > +#define MT6360_PMU_BUCK1_IRQ (0xDC) > >> > +#define MT6360_PMU_BUCK2_IRQ (0xDD) > >> > +#define MT6360_PMU_LDO_IRQ1 (0xDE) > >> > +#define MT6360_PMU_LDO_IRQ2 (0xDF) > >> > +#define MT6360_PMU_CHG_STAT1 (0xE0) > >> > +#define MT6360_PMU_CHG_STAT2 (0xE1) > >> > +#define MT6360_PMU_CHG_STAT3 (0xE2) > >> > +#define MT6360_PMU_CHG_STAT4 (0xE3) > >> > +#define MT6360_PMU_CHG_STAT5 (0xE4) > >> > +#define MT6360_PMU_CHG_STAT6 (0xE5) > >> > +#define MT6360_PMU_QC_STAT (0xE6) > >> > +#define MT6360_PMU_FOD_STAT (0xE7) > >> > +#define MT6360_PMU_BASE_STAT (0xE8) > >> > +#define MT6360_PMU_FLED_STAT1 (0xE9) > >> > +#define MT6360_PMU_FLED_STAT2 (0xEA) > >> > +#define MT6360_PMU_RGB_STAT (0xEB) > >> > +#define MT6360_PMU_BUCK1_STAT (0xEC) > >> > +#define MT6360_PMU_BUCK2_STAT (0xED) > >> > +#define MT6360_PMU_LDO_STAT1 (0xEE) > >> > +#define MT6360_PMU_LDO_STAT2 (0xEF) > >> > +#define MT6360_PMU_CHG_MASK1 (0xF0) > >> > +#define MT6360_PMU_CHG_MASK2 (0xF1) > >> > +#define MT6360_PMU_CHG_MASK3 (0xF2) > >> > +#define MT6360_PMU_CHG_MASK4 (0xF3) > >> > +#define MT6360_PMU_CHG_MASK5 (0xF4) > >> > +#define MT6360_PMU_CHG_MASK6 (0xF5) > >> > +#define MT6360_PMU_QC_MASK (0xF6) > >> > +#define MT6360_PMU_FOD_MASK (0xF7) > >> > +#define MT6360_PMU_BASE_MASK (0xF8) > >> > +#define MT6360_PMU_FLED_MASK1 (0xF9) > >> > +#define MT6360_PMU_FLED_MASK2 (0xFA) > >> > +#define MT6360_PMU_FAULTB_MASK (0xFB) > >> > +#define MT6360_PMU_BUCK1_MASK (0xFC) > >> > +#define MT6360_PMU_BUCK2_MASK (0xFD) > >> > +#define MT6360_PMU_LDO_MASK1 (0xFE) > >> > +#define MT6360_PMU_LDO_MASK2 (0xFF) > >> > +#define MT6360_PMU_MAXREG (MT6360_PMU_LDO_MASK2) > >> > + > >> > + > >> > +/* MT6360_PMU_IRQ_SET */ > >> > +#define MT6360_PMU_IRQ_REGNUM (MT6360_PMU_LDO_IRQ2 - > >> > MT6360_PMU_CHG_IRQ1 + 1) > >> > +#define MT6360_IRQ_RETRIG BIT(2) > >> > + > >> > +#define CHIP_VEN_MASK (0xF0) > >> > +#define CHIP_VEN_MT6360 (0x50) > >> > +#define CHIP_REV_MASK (0x0F) > >> > + > >> > +/* IRQ definitions */ > >> > >> Remove this please. > >> > >> > +struct mt6360_pmu_irq_desc { > >> > + const char *name; > >> > + irq_handler_t irq_handler; > >> > +}; > >> > >> Where is this used? > >> > >> > +#define MT6360_DT_VALPROP(name, type) \ > >> > + {#name, offsetof(type, name)} > >> > >> Where is this used? > >> > >> > +struct mt6360_val_prop { > >> > + const char *name; > >> > + size_t offset; > >> > +}; > >> > + > >> > +static inline void mt6360_dt_parser_helper(struct device_node *np, void > >> > *data, > >> > + const struct mt6360_val_prop > >> > *props, > >> > + int prop_cnt) > >> > +{ > >> > + int i; > >> > + > >> > + for (i = 0; i < prop_cnt; i++) { > >> > + if (unlikely(!props[i].name)) > >> > + continue; > >> > + of_property_read_u32(np, props[i].name, data + > >> > props[i].offset); > >> > + } > >> > +} > >> > >> What are you using this for? Why is the standard API not sufficient? > >> > >> > +#define MT6360_PDATA_VALPROP(name, type, reg, shift, mask, func, base) > >> > \ > >> > + {offsetof(type, name), reg, shift, mask, func, > >> > base} > >> > >> Where is this used? > >> > >> > +struct mt6360_pdata_prop { > >> > + size_t offset; > >> > + u8 reg; > >> > + u8 shift; > >> > + u8 mask; > >> > + u32 (*transform)(u32 val); > >> > + u8 base; > >> > +}; > >> > + > >> > +static inline int mt6360_pdata_apply_helper(void *context, void > >> > *pdata, > >> > + const struct mt6360_pdata_prop > >> > *prop, > >> > + int prop_cnt) > >> > +{ > >> > + int i, ret; > >> > + u32 val; > >> > + > >> > + for (i = 0; i < prop_cnt; i++) { > >> > + val = *(u32 *)(pdata + prop[i].offset); > >> > + if (prop[i].transform) > >> > + val = prop[i].transform(val); > >> > + val += prop[i].base; > >> > + ret = regmap_update_bits(context, > >> > + prop[i].reg, prop[i].mask, val << > >> > prop[i].shift); > >> > + if (ret < 0) > >> > + return ret; > >> > + } > >> > + return 0; > >> > +} > >> > >> Where is this used? What does it do? > >> > >> > +#endif /* __MT6360_PRIVATE_H__ */ > >> > diff --git a/include/linux/mfd/mt6360.h b/include/linux/mfd/mt6360.h > >> > new file mode 100644 > >> > index 0000000..ba2e80a > >> > --- /dev/null > >> > +++ b/include/linux/mfd/mt6360.h > >> > @@ -0,0 +1,33 @@ > >> > +/* SPDX-License-Identifier: GPL-2.0 */ > >> > +/* > >> > + * Copyright (c) 2019 MediaTek Inc. > >> > + */ > >> > + > >> > +#ifndef __MT6360_H__ > >> > +#define __MT6360_H__ > >> > + > >> > +#include > >> > + > >> > +enum { > >> > + MT6360_SLAVE_PMU = 0, > >> > + MT6360_SLAVE_PMIC, > >> > + MT6360_SLAVE_LDO, > >> > + MT6360_SLAVE_TCPC, > >> > + MT6360_SLAVE_MAX, > >> > +}; > >> > + > >> > +#define MT6360_PMU_SLAVEID (0x34) > >> > +#define MT6360_PMIC_SLAVEID (0x1A) > >> > +#define MT6360_LDO_SLAVEID (0x64) > >> > +#define MT6360_TCPC_SLAVEID (0x4E) > >> > >> What kind of slave ID? I2C address? > >> > >> > +struct mt6360_pmu_info { > >> > + struct i2c_client *i2c[MT6360_SLAVE_MAX]; > >> > + struct device *dev; > >> > >> > + struct regmap *regmap; > >> > + struct regmap_irq_chip_data *irq_data; > >> > + struct regmap_irq_chip irq_chip; > >> > + unsigned int chip_rev; > >> > >> Why are you saving these? > >> > >> Where do you reuse them? > >> > >> > +}; > >> > + > >> > +#endif /* __MT6360_H__ */ > >> > > -- Lee Jones [???] Linaro Services Technical Lead Linaro.org ? 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<20191004133324.GE18429@dell> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191016_030442_701300_476519A5 X-CRM114-Status: GOOD ( 28.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: gene_chen@richtek.com, linux-kernel@vger.kernel.org, cy_huang@richtek.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, Wilma.Wu@mediatek.com, linux-arm-kernel@lists.infradead.org, shufan_lee@richtek.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gVHVlLCAxNSBPY3QgMjAxOSwgR2VuZSBDaGVuIHdyb3RlOgoKPiBIaSBMZWUsCj4gCj4gd2Ug ZmluZCBPRl9NRkRfQ0VMTCBpcyBub3QgZGVmaW5lZCBpbiBtZmQvY29yZS5oLCB3aGljaCBpcyBy ZWFkeSB0bwo+IG1lcmdlIHRvIG5leHQga2VybmVsIHZlcnNpb24KPiBodHRwczovL2tlcm5lbC5n b29nbGVzb3VyY2UuY29tL3B1Yi9zY20vbGludXgva2VybmVsL2dpdC9uZXh0L2xpbnV4LW5leHQt aGlzdG9yeS8rL21hc3Rlci9OZXh0L21lcmdlLmxvZwoKSXQncyBoZXJlOgoKTWVyZ2luZyBtZmQv Zm9yLW1mZC1uZXh0ICgzOGE2ZmM2M2EzZWEgbWZkOiBkYjg1MDAtcHJjbXU6IEV4YW1wbGUgdXNp bmcgbmV3IE9GX01GRF9DRUxML01GRF9DRUxMX0JBU0lDIE1BQ1JPcykKJCBnaXQgbWVyZ2UgbWZk L2Zvci1tZmQtbmV4dApNZXJnZSBtYWRlIGJ5IHRoZSAncmVjdXJzaXZlJyBzdHJhdGVneS4KIGRy aXZlcnMvbWZkL2FiODUwMC1jb3JlLmMgICAgfCAxMzggKysrKysrKysrKysrKy0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLQogZHJpdmVycy9tZmQvZGI4NTAwLXByY211LmMgICB8ICAyMSAr KystLS0tCiBkcml2ZXJzL21mZC9pbnRlbC1scHNzLXBjaS5jIHwgIDI4ICsrKysrKy0tLQogZHJp dmVycy9tZmQvaXBhcS1taWNyby5jICAgICB8ICAgNiArLQogZHJpdmVycy9tZmQvcms4MDguYyAg ICAgICAgICB8ICAyMiArKy0tLS0tCiBpbmNsdWRlL2xpbnV4L21mZC9jb3JlLmggICAgIHwgIDI5 ICsrKysrKysrKyAgICAgICAgICAgICAgICA8PT09PT0gW1RISVMgT05FXQogaW5jbHVkZS9saW51 eC9tZmQvcms4MDguaCAgICB8ICAgMiArLQogNyBmaWxlcyBjaGFuZ2VkLCAxMDUgaW5zZXJ0aW9u cygrKSwgMTQxIGRlbGV0aW9ucygtKQoKaHR0cHM6Ly9rZXJuZWwuZ29vZ2xlc291cmNlLmNvbS9w dWIvc2NtL2xpbnV4L2tlcm5lbC9naXQvbmV4dC9saW51eC1uZXh0LWhpc3RvcnkvKy9tYXN0ZXIv TmV4dC9tZXJnZS5sb2cjNDQ3MAoKPiBtYXkgaSBhc2sgaG93IGNhbiBpIHVwc3RyZWFtIHdpdGhv dXQgdGhpcyBkZWZpbml0aW9uPwo+IGUuZy4gd2UgcHVsbCB0aGlzIHBhdGNoIGFuZCBidWlsZCBw YXNzLCBuZXcgcGF0Y2ggd2l0aG91dCBhZGQgbWFjcm8gZGVmaW5lCj4gCj4gMjAxOS0xMC0wOCAy OjI0IEdNVCswODowMCwgR2VuZSBDaGVuIDxnZW5lLmNoZW4ucmljaHRla0BnbWFpbC5jb20+Ogo+ ID4gSGkgSm9uZXMsCj4gPgo+ID4gVGhhbmtzIGZvciByZXZpZXcsIHdlIHdpbGwgZml4IHNvbWUg Y29tbWVudCB3aGljaCB5b3VyIHN1Z2dlc3Rpb24gaW4gbmV4dAo+ID4gcGF0Y2gKPiA+Cj4gPiBM ZWUgSm9uZXMgPGxlZS5qb25lc0BsaW5hcm8ub3JnPiDmlrwgMjAxOeW5tDEw5pyINOaXpSDpgLHk upQg5LiL5Y2IOTozM+Wvq+mBk++8mgo+ID4+Cj4gPj4gV29sZnJhbSwKPiA+Pgo+ID4+IFdvdWxk IHlvdSBiZSBraW5kIGVub3VnaCB0byBncmVwIGZvciB5b3VyIG5hbWUgYmVsb3c/Cj4gPj4KPiA+ PiBPbiBUdWUsIDI0IFNlcCAyMDE5LCBHZW5lIENoZW4gd3JvdGU6Cj4gPj4KPiA+PiA+IEZyb206 IEdlbmUgQ2hlbiA8Z2VuZV9jaGVuQHJpY2h0ZWsuY29tPgo+ID4+ID4KPiA+PiA+IEFkZCBtZmQg ZHJpdmVyIGZvciBtdDYzNjAgcG1pYyBjaGlwIGluY2x1ZGUKPiA+PiA+IEJhdHRlcnkgQ2hhcmdl ci9VU0JfUEQvRmxhc2ggTEVEL1JHQiBMRUQvTERPL0J1Y2sKPiA+PiA+Cj4gPj4gPiBTaWduZWQt b2ZmLWJ5OiBHZW5lIENoZW4gPGdlbmVfY2hlbkByaWNodGVrLmNvbQo+ID4+ID4gLS0tCj4gPj4g PiAgZHJpdmVycy9tZmQvS2NvbmZpZyAgICAgICAgICAgICAgICB8ICAxMiArCj4gPj4gPiAgZHJp dmVycy9tZmQvTWFrZWZpbGUgICAgICAgICAgICAgICB8ICAgMSArCj4gPj4gPiAgZHJpdmVycy9t ZmQvbXQ2MzYwLWNvcmUuYyAgICAgICAgICB8IDQ2Mwo+ID4+ID4gKysrKysrKysrKysrKysrKysr KysrKysrKysrKysrKysrKysrKwo+ID4+ID4gIGluY2x1ZGUvbGludXgvbWZkL210NjM2MC1wcml2 YXRlLmggfCAyNzkgKysrKysrKysrKysrKysrKysrKysrKwo+ID4+ID4gIGluY2x1ZGUvbGludXgv bWZkL210NjM2MC5oICAgICAgICAgfCAgMzMgKysrCj4gPj4gPiAgNSBmaWxlcyBjaGFuZ2VkLCA3 ODggaW5zZXJ0aW9ucygrKQo+ID4+ID4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBkcml2ZXJzL21mZC9t dDYzNjAtY29yZS5jCj4gPj4gPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGluY2x1ZGUvbGludXgvbWZk L210NjM2MC1wcml2YXRlLmgKPiA+PiA+ICBjcmVhdGUgbW9kZSAxMDA2NDQgaW5jbHVkZS9saW51 eC9tZmQvbXQ2MzYwLmgKPiA+PiA+Cj4gPj4gPiBjaGFuZ2Vsb2dzIGJldHdlZW4gdjEgJiB2Mgo+ ID4+ID4gLSBpbmNsdWRlIG1pc3NpbmcgaGVhZGVyIGZpbGUKPiA+PiA+Cj4gPj4gPiBjaGFuZ2Vs b2dzIGJldHdlZW4gdjIgJiB2Mwo+ID4+ID4gLSBhZGQgY2hhbmdlbG9ncwo+ID4+ID4KPiA+PiA+ IGRpZmYgLS1naXQgYS9kcml2ZXJzL21mZC9LY29uZmlnIGIvZHJpdmVycy9tZmQvS2NvbmZpZwo+ ID4+ID4gaW5kZXggZjEyOWY5Ni4uYTQyMmM3NiAxMDA2NDQKPiA+PiA+IC0tLSBhL2RyaXZlcnMv bWZkL0tjb25maWcKPiA+PiA+ICsrKyBiL2RyaXZlcnMvbWZkL0tjb25maWcKPiA+PiA+IEBAIC04 NjIsNiArODYyLDE4IEBAIGNvbmZpZyBNRkRfTUFYODk5OAo+ID4+ID4gICAgICAgICBhZGRpdGlv bmFsIGRyaXZlcnMgbXVzdCBiZSBlbmFibGVkIGluIG9yZGVyIHRvIHVzZSB0aGUKPiA+PiA+IGZ1 bmN0aW9uYWxpdHkKPiA+PiA+ICAgICAgICAgb2YgdGhlIGRldmljZS4KPiA+PiA+Cj4gPj4gPiAr Y29uZmlnIE1GRF9NVDYzNjAKPiA+PiA+ICsgICAgIHRyaXN0YXRlICJNZWRpYXRlayBNVDYzNjAg U3ViUE1JQyIKPiA+PiA+ICsgICAgIHNlbGVjdCBNRkRfQ09SRQo+ID4+ID4gKyAgICAgc2VsZWN0 IFJFR01BUF9JMkMKPiA+PiA+ICsgICAgIHNlbGVjdCBSRUdNQVBfSVJRCj4gPj4gPiArICAgICBk ZXBlbmRzIG9uIEkyQwo+ID4+ID4gKyAgICAgaGVscAo+ID4+ID4gKyAgICAgICBTYXkgWSBoZXJl IHRvIGVuYWJsZSBNVDYzNjAgUE1VL1BNSUMvTERPIGZ1bmN0aW9uYWwgc3VwcG9ydC4KPiA+PiA+ ICsgICAgICAgUE1VIHBhcnQgaW5jbHVkZSBjaGFyZ2VyLCBmbGFzaGxpZ2h0LCByZ2IgbGVkCj4g Pj4gPiArICAgICAgIFBNSUMgcGFydCBpbmNsdWRlIDItY2hhbm5lbCBCVUNLcyBhbmQgMi1jaGFu bmVsIExET3MKPiA+PiA+ICsgICAgICAgTERPIHBhcnQgaW5jbHVkZSA0LWNoYW5uZWwgTERPcwo+ ID4+Cj4gPj4gICAgICAgICAgIFBNVSBwYXJ0IGluY2x1ZGVzIENoYXJnZXIsIEZsYXNobGlnaHQs IFJHQiBhbmQgTEVECj4gPj4gICAgICAgICAgIFBNSUMgcGFydCBpbmNsdWRlcyAyLWNoYW5uZWwg QlVDS3MgYW5kIDItY2hhbm5lbCBMRE9zCj4gPj4gICAgICAgICAgIExETyBwYXJ0IGluY2x1ZGVz IDQtY2hhbm5lbCBMRE9zCj4gPj4KPiA+Cj4gPiBBQ0suIFJHQiBMRUQgaXMgb25lIG9mIGluZGlj YXRvciBsaWdodCwgb25seSBzaW5nbGUgZmVhdHVyZQo+ID4KPiA+PiA+ICBjb25maWcgTUZEX01U NjM5Nwo+ID4+ID4gICAgICAgdHJpc3RhdGUgIk1lZGlhVGVrIE1UNjM5NyBQTUlDIFN1cHBvcnQi Cj4gPj4gPiAgICAgICBzZWxlY3QgTUZEX0NPUkUKPiA+PiA+IGRpZmYgLS1naXQgYS9kcml2ZXJz L21mZC9NYWtlZmlsZSBiL2RyaXZlcnMvbWZkL01ha2VmaWxlCj4gPj4gPiBpbmRleCBmMDI2YWRh Li43N2E4ZjBiIDEwMDY0NAo+ID4+ID4gLS0tIGEvZHJpdmVycy9tZmQvTWFrZWZpbGUKPiA+PiA+ ICsrKyBiL2RyaXZlcnMvbWZkL01ha2VmaWxlCj4gPj4gPiBAQCAtMjQxLDYgKzI0MSw3IEBAIG9i ai0kKENPTkZJR19JTlRFTF9TT0NfUE1JQykgICAgICArPQo+ID4+ID4gaW50ZWwtc29jLXBtaWMu bwo+ID4+ID4gIG9iai0kKENPTkZJR19JTlRFTF9TT0NfUE1JQ19CWFRXQykgICArPSBpbnRlbF9z b2NfcG1pY19ieHR3Yy5vCj4gPj4gPiAgb2JqLSQoQ09ORklHX0lOVEVMX1NPQ19QTUlDX0NIVFdD KSAgICs9IGludGVsX3NvY19wbWljX2NodHdjLm8KPiA+PiA+ICBvYmotJChDT05GSUdfSU5URUxf U09DX1BNSUNfQ0hURENfVEkpICAgICAgICArPQo+ID4+ID4gaW50ZWxfc29jX3BtaWNfY2h0ZGNf dGkubwo+ID4+ID4gK29iai0kKENPTkZJR19NRkRfTVQ2MzYwKSAgICAgKz0gbXQ2MzYwLWNvcmUu bwo+ID4+ID4gIG9iai0kKENPTkZJR19NRkRfTVQ2Mzk3KSAgICAgKz0gbXQ2Mzk3LWNvcmUubwo+ ID4+ID4KPiA+PiA+ICBvYmotJChDT05GSUdfTUZEX0FMVEVSQV9BMTBTUikgICAgICAgKz0gYWx0 ZXJhLWExMHNyLm8KPiA+PiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL21mZC9tdDYzNjAtY29yZS5j IGIvZHJpdmVycy9tZmQvbXQ2MzYwLWNvcmUuYwo+ID4+ID4gbmV3IGZpbGUgbW9kZSAxMDA2NDQK PiA+PiA+IGluZGV4IDAwMDAwMDAuLmQzNTgwNjE4Cj4gPj4gPiAtLS0gL2Rldi9udWxsCj4gPj4g PiArKysgYi9kcml2ZXJzL21mZC9tdDYzNjAtY29yZS5jCj4gPj4gPiBAQCAtMCwwICsxLDQ2MyBA QAo+ID4+ID4gKy8vIFNQRFgtTGljZW5zZS1JZGVudGlmaWVyOiBHUEwtMi4wCj4gPj4gPiArLyoK PiA+PiA+ICsgKiBDb3B5cmlnaHQgKGMpIDIwMTkgTWVkaWFUZWsgSW5jLgo+ID4+ID4gKyAqLwo+ ID4+ID4gKwo+ID4+ID4gKyNpbmNsdWRlIDxsaW51eC9pMmMuaD4KPiA+PiA+ICsjaW5jbHVkZSA8 bGludXgvaW5pdC5oPgo+ID4+ID4gKyNpbmNsdWRlIDxsaW51eC9rZXJuZWwuaD4KPiA+PiA+ICsj aW5jbHVkZSA8bGludXgvbWZkL2NvcmUuaD4KPiA+PiA+ICsjaW5jbHVkZSA8bGludXgvbW9kdWxl Lmg+Cj4gPj4gPiArI2luY2x1ZGUgPGxpbnV4L29mX2lycS5oPgo+ID4+ID4gKyNpbmNsdWRlIDxs aW51eC9vZl9wbGF0Zm9ybS5oPgo+ID4+ID4gKyNpbmNsdWRlIDxsaW51eC92ZXJzaW9uLmg+Cj4g Pj4gPiArCj4gPj4gPiArI2luY2x1ZGUgPGxpbnV4L21mZC9tdDYzNjAuaD4KPiA+PiA+ICsjaW5j bHVkZSA8bGludXgvbWZkL210NjM2MC1wcml2YXRlLmg+Cj4gPj4gPiArCj4gPj4gPiArLyogcmVn IDAgLT4gMCB+IDcgKi8KPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9DSEdfVFJFR19FVlQgICAgICAg ICAgKDQpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfQ0hHX0FJQ1JfRVZUICAgICAgICAgICg1KQo+ ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0NIR19NSVZSX0VWVCAgICAgICAgICAoNikKPiA+PiA+ICsj ZGVmaW5lIE1UNjM2MF9QV1JfUkRZX0VWVCAgICAgICAgICAgKDcpCj4gPj4gPiArLyogUkVHIDEg LT4gOCB+IDE1ICovCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfQ0hHX0JBVFNZU1VWX0VWVCAgICAg ICAgICAgICAgKDkpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfRkxFRF9DSEdfVklOT1ZQX0VWVCAg ICgxMSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9DSEdfVlNZU1VWX0VWVCAgICAgICAgICAgICAg ICAoMTIpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfQ0hHX1ZTWVNPVl9FVlQgICAgICAgICAgICAg ICAgKDEzKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0NIR19WQkFUT1ZfRVZUICAgICAgICAgICAg ICAgICgxNCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9DSEdfVkJVU09WX0VWVCAgICAgICAgICAg ICAgICAoMTUpCj4gPj4gPiArLyogUkVHIDIgLT4gMTYgfiAyMyAqLwo+ID4+ID4gKy8qIFJFRyAz IC0+IDI0IH4gMzEgKi8KPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9XRF9QTVVfREVUICAgICAgICAg ICAgKDI1KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1dEX1BNVV9ET05FICAgICAgICAgICAoMjYp Cj4gPj4gPiArI2RlZmluZSBNVDYzNjBfQ0hHX1RNUkkgICAgICAgICAgICAgICAgICAgICAgKDI3 KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0NIR19BRFBCQURJICAgICAgICAgICAoMjkpCj4gPj4g PiArI2RlZmluZSBNVDYzNjBfQ0hHX1JWUEkgICAgICAgICAgICAgICAgICAgICAgKDMwKQo+ID4+ ID4gKyNkZWZpbmUgTVQ2MzYwX09UUEkgICAgICAgICAgICAgICAgICAoMzEpCj4gPj4gPiArLyog UkVHIDQgLT4gMzIgfiAzOSAqLwo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0NIR19BSUNDTUVBU0wg ICAgICAgICAoMzIpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfQ0hHREVUX0RPTkVJICAgICAgICAg ICgzNCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9XRFRNUkkgICAgICAgICAgICAgICAgICAgICAg ICAoMzUpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfU1NGSU5JU0hJICAgICAgICAgICAgICgzNikK PiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9DSEdfUkVDSEdJICAgICAgICAgICAgKDM3KQo+ID4+ID4g KyNkZWZpbmUgTVQ2MzYwX0NIR19URVJNSSAgICAgICAgICAgICAoMzgpCj4gPj4gPiArI2RlZmlu ZSBNVDYzNjBfQ0hHX0lFT0NJICAgICAgICAgICAgICgzOSkKPiA+PiA+ICsvKiBSRUcgNSAtPiA0 MCB+IDQ3ICovCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUFVNUFhfRE9ORUkgICAgICAgICAgICg0 MCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9CQVRfT1ZQX0FEQ19FVlQgICAgICAgICAgICAgICAo NDEpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfVFlQRUNfT1RQX0VWVCAgICAgICAgICg0MikKPiA+ PiA+ICsjZGVmaW5lIE1UNjM2MF9BRENfV0FLRVVQX0VWVCAgICAgICAgICAgICAgICAoNDMpCj4g Pj4gPiArI2RlZmluZSBNVDYzNjBfQURDX0RPTkVJICAgICAgICAgICAgICg0NCkKPiA+PiA+ICsj ZGVmaW5lIE1UNjM2MF9CU1RfQkFUVVZJICAgICAgICAgICAgKDQ1KQo+ID4+ID4gKyNkZWZpbmUg TVQ2MzYwX0JTVF9WQlVTT1ZJICAgICAgICAgICAoNDYpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBf QlNUX09MUEkgICAgICAgICAgICAgICAgICAgICAgKDQ3KQo+ID4+ID4gKy8qIFJFRyA2IC0+IDQ4 IH4gNTUgKi8KPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9BVFRBQ0hfSSAgICAgICAgICAgICAgICAg ICAgICAoNDgpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfREVUQUNIX0kgICAgICAgICAgICAgICAg ICAgICAgKDQ5KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1FDMzBfU1RQRE9ORSAgICAgICAgICAo NTEpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUUNfVkJVU0RFVF9ET05FICAgICAgICAgICAgICAg KDUyKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0hWRENQX0RFVCAgICAgICAgICAgICAoNTMpCj4g Pj4gPiArI2RlZmluZSBNVDYzNjBfQ0hHREVUSSAgICAgICAgICAgICAgICAgICAgICAgKDU0KQo+ ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0RDRFRJICAgICAgICAgICAgICAgICAoNTUpCj4gPj4gPiAr LyogUkVHIDcgLT4gNTYgfiA2MyAqLwo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0ZPRF9ET05FX0VW VCAgICAgICAgICAoNTYpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfRk9EX09WX0VWVCAgICAgICAg ICAgICg1NykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9DSFJERVRfVVZQX0VWVCAgICAgICAgICAg ICAgICAoNTgpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfQ0hSREVUX09WUF9FVlQgICAgICAgICAg ICAgICAgKDU5KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0NIUkRFVF9FWFRfRVZUICAgICAgICAg ICAgICAgICg2MCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9GT0RfTFJfRVZUICAgICAgICAgICAg KDYxKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0ZPRF9IUl9FVlQgICAgICAgICAgICAoNjIpCj4g Pj4gPiArI2RlZmluZSBNVDYzNjBfRk9EX0RJU0NIR19GQUlMX0VWVCAgICg2MykKPiA+PiA+ICsv KiBSRUcgOCAtPiA2NCB+IDcxICovCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfVVNCSURfRVZUICAg ICAgICAgICAgICg2NCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9BUFdEVFJTVF9FVlQgICAgICAg ICAgKDY1KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0VOX0VWVCAgICAgICAgICAgICAgICAgICAg ICAgICg2NikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9RT05CX1JTVF9FVlQgICAgICAgICAgKDY3 KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX01SU1RCX0VWVCAgICAgICAgICAgICAoNjgpCj4gPj4g PiArI2RlZmluZSBNVDYzNjBfT1RQX0VWVCAgICAgICAgICAgICAgICAgICAgICAgKDY5KQo+ID4+ ID4gKyNkZWZpbmUgTVQ2MzYwX1ZEREFPVl9FVlQgICAgICAgICAgICAoNzApCj4gPj4gPiArI2Rl ZmluZSBNVDYzNjBfU1lTVVZfRVZUICAgICAgICAgICAgICg3MSkKPiA+PiA+ICsvKiBSRUcgOSAt PiA3MiB+IDc5ICovCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfRkxFRF9TVFJCUElOX0VWVCAgICAg ICAgICAgICAgKDcyKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0ZMRURfVE9SUElOX0VWVCAgICAg ICAgICAgICAgICg3MykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9GTEVEX1RYX0VWVCAgICAgICAg ICAgKDc0KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0ZMRURfTFZGX0VWVCAgICAgICAgICAoNzUp Cj4gPj4gPiArI2RlZmluZSBNVDYzNjBfRkxFRDJfU0hPUlRfRVZUICAgICAgICAgICAgICAgKDc4 KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0ZMRUQxX1NIT1JUX0VWVCAgICAgICAgICAgICAgICg3 OSkKPiA+PiA+ICsvKiBSRUcgMTAgLT4gODAgfiA4NyAqLwo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYw X0ZMRUQyX1NUUkJfRVZUICAgICAgICAgICAgICAgICg4MCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2 MF9GTEVEMV9TVFJCX0VWVCAgICAgICAgICAgICAgICAoODEpCj4gPj4gPiArI2RlZmluZSBNVDYz NjBfRkxFRDJfU1RSQl9UT19FVlQgICAgICg4MikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9GTEVE MV9TVFJCX1RPX0VWVCAgICAgKDgzKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0ZMRUQyX1RPUl9F VlQgICAgICAgICAoODQpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfRkxFRDFfVE9SX0VWVCAgICAg ICAgICg4NSkKPiA+PiA+ICsvKiBSRUcgMTEgLT4gODggfiA5NSAqLwo+ID4+ID4gKy8qIFJFRyAx MiAtPiA5NiB+IDEwMyAqLwo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0JVQ0sxX1BHQl9FVlQgICAg ICAgICAoOTYpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfQlVDSzFfT0NfRVZUICAgICAgICAgICgx MDApCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfQlVDSzFfT1ZfRVZUICAgICAgICAgICgxMDEpCj4g Pj4gPiArI2RlZmluZSBNVDYzNjBfQlVDSzFfVVZfRVZUICAgICAgICAgICgxMDIpCj4gPj4gPiAr LyogUkVHIDEzIC0+IDEwNCB+IDExMSAqLwo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0JVQ0syX1BH Ql9FVlQgICAgICAgICAoMTA0KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0JVQ0syX09DX0VWVCAg ICAgICAgICAoMTA4KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0JVQ0syX09WX0VWVCAgICAgICAg ICAoMTA5KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0JVQ0syX1VWX0VWVCAgICAgICAgICAoMTEw KQo+ID4+ID4gKy8qIFJFRyAxNCAtPiAxMTIgfiAxMTkgKi8KPiA+PiA+ICsjZGVmaW5lIE1UNjM2 MF9MRE8xX09DX0VWVCAgICAgICAgICAgKDExMykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9MRE8y X09DX0VWVCAgICAgICAgICAgKDExNCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9MRE8zX09DX0VW VCAgICAgICAgICAgKDExNSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9MRE81X09DX0VWVCAgICAg ICAgICAgKDExNykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9MRE82X09DX0VWVCAgICAgICAgICAg KDExOCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9MRE83X09DX0VWVCAgICAgICAgICAgKDExOSkK PiA+PiA+ICsvKiBSRUcgMTUgLT4gMTIwIH4gMTI3ICovCj4gPj4gPiArI2RlZmluZSBNVDYzNjBf TERPMV9QR0JfRVZUICAgICAgICAgICgxMjEpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfTERPMl9Q R0JfRVZUICAgICAgICAgICgxMjIpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfTERPM19QR0JfRVZU ICAgICAgICAgICgxMjMpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfTERPNV9QR0JfRVZUICAgICAg ICAgICgxMjUpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfTERPNl9QR0JfRVZUICAgICAgICAgICgx MjYpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfTERPN19QR0JfRVZUICAgICAgICAgICgxMjcpCj4g Pj4gPiArCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUkVHTUFQX0lSUV9SRUcoX2lycV9ldnQpICAg ICAgICAgICAgICBcCj4gPj4gPiArICAgICBSRUdNQVBfSVJRX1JFRyhfaXJxX2V2dCwgKF9pcnFf ZXZ0KSAvIDgsIEJJVCgoX2lycV9ldnQpICUgOCkpCj4gPj4gPiArCj4gPj4gPiArI2RlZmluZSBN VDYzNjBfTUZEX0NFTEwoX25hbWUpICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgXAo+ID4+ID4gKyAgICAgeyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICBcCj4gPj4gPiArICAgICAgICAgICAgIC5uYW1lID0gI19uYW1lLCAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIFwKPiA+PiA+ICsgICAgICAgICAgICAgLm9m X2NvbXBhdGlibGUgPSAibWVkaWF0ZWssIiAjX25hbWUsICAgICAgICAgICAgXAo+ID4+ID4gKyAg ICAgICAgICAgICAubnVtX3Jlc291cmNlcyA9IEFSUkFZX1NJWkUoX25hbWUjI19yZXNvdXJjZXMp LCBcCj4gPj4gPiArICAgICAgICAgICAgIC5yZXNvdXJjZXMgPSBfbmFtZSMjX3Jlc291cmNlcywg ICAgICAgICAgICAgICAgIFwKPiA+PiA+ICsgICAgIH0KPiA+Pgo+ID4+IFBsZWFzZSBkbyBub3Qg cm9sbCB5b3VyIG93biBNQUNST1MgbGlrZSB0aGlzLiAgSWYgdGhleSBhcmUgaGVscGZ1bCBmb3IK PiA+PiB5b3UsIHRoZXkgYXJlIGxpa2VseSB0byBiZSBoZWxwZnVsIGZvciBvdGhlcnMuICBIb3dl dmVyLCB0aGlzIGlzIHlvdXIKPiA+PiBsdWNreSBkYXksIGFzIHdlJ3ZlIGJlZW4gaGVyZSBiZWZv cmUuICBQbGVhc2UgcmViYXNlIG9udG8gdGhlIE1GRCB0cmVlCj4gPj4gd2hlcmUgeW91IHdpbGwg ZmluZCBzb21lIHByZS1hdXRob3JlZCBtYWNyb3Mgd2hpY2ggYXJlbid0IHRvbwo+ID4+IGRpc3Np bWlsYXIgdG8gdGhpcyBvbmUuICBQbGVhc2UgdXNlIG9uZSBvZiB0aG9zZSBpbnN0ZWFkLgo+ID4+ Cj4gPgo+ID4gQUNLCj4gPgo+ID4+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcmVnbWFwX2lycSBt dDYzNjBfcG11X2lycXNbXSA9ICB7Cj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUco TVQ2MzYwX0NIR19UUkVHX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUco TVQ2MzYwX0NIR19BSUNSX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUco TVQ2MzYwX0NIR19NSVZSX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUco TVQ2MzYwX1BXUl9SRFlfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhN VDYzNjBfQ0hHX0JBVFNZU1VWX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9S RUcoTVQ2MzYwX0ZMRURfQ0hHX1ZJTk9WUF9FVlQpLAo+ID4+ID4gKyAgICAgTVQ2MzYwX1JFR01B UF9JUlFfUkVHKE1UNjM2MF9DSEdfVlNZU1VWX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVH TUFQX0lSUV9SRUcoTVQ2MzYwX0NIR19WU1lTT1ZfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9S RUdNQVBfSVJRX1JFRyhNVDYzNjBfQ0hHX1ZCQVRPVl9FVlQpLAo+ID4+ID4gKyAgICAgTVQ2MzYw X1JFR01BUF9JUlFfUkVHKE1UNjM2MF9DSEdfVkJVU09WX0VWVCksCj4gPj4gPiArICAgICBNVDYz NjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX1dEX1BNVV9ERVQpLAo+ID4+ID4gKyAgICAgTVQ2MzYw X1JFR01BUF9JUlFfUkVHKE1UNjM2MF9XRF9QTVVfRE9ORSksCj4gPj4gPiArICAgICBNVDYzNjBf UkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0NIR19UTVJJKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdN QVBfSVJRX1JFRyhNVDYzNjBfQ0hHX0FEUEJBREkpLAo+ID4+ID4gKyAgICAgTVQ2MzYwX1JFR01B UF9JUlFfUkVHKE1UNjM2MF9DSEdfUlZQSSksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lS UV9SRUcoTVQ2MzYwX09UUEkpLAo+ID4+ID4gKyAgICAgTVQ2MzYwX1JFR01BUF9JUlFfUkVHKE1U NjM2MF9DSEdfQUlDQ01FQVNMKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhN VDYzNjBfQ0hHREVUX0RPTkVJKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhN VDYzNjBfV0RUTVJJKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBf U1NGSU5JU0hJKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfQ0hH X1JFQ0hHSSksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0NIR19U RVJNSSksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0NIR19JRU9D SSksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX1BVTVBYX0RPTkVJ KSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfQ0hHX1RSRUdfRVZU KSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfQkFUX09WUF9BRENf RVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfVFlQRUNfT1RQ X0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0FEQ19XQUtF VVBfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfQURDX0RP TkVJKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfQlNUX0JBVFVW SSksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0JTVF9WQlVTT1ZJ KSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfQlNUX09MUEkpLAo+ ID4+ID4gKyAgICAgTVQ2MzYwX1JFR01BUF9JUlFfUkVHKE1UNjM2MF9BVFRBQ0hfSSksCj4gPj4g PiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0RFVEFDSF9JKSwKPiA+PiA+ICsg ICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfUUMzMF9TVFBET05FKSwKPiA+PiA+ICsg ICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfUUNfVkJVU0RFVF9ET05FKSwKPiA+PiA+ ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfSFZEQ1BfREVUKSwKPiA+PiA+ICsg ICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfQ0hHREVUSSksCj4gPj4gPiArICAgICBN VDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0RDRFRJKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9S RUdNQVBfSVJRX1JFRyhNVDYzNjBfRk9EX0RPTkVfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9S RUdNQVBfSVJRX1JFRyhNVDYzNjBfRk9EX09WX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVH TUFQX0lSUV9SRUcoTVQ2MzYwX0NIUkRFVF9VVlBfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9S RUdNQVBfSVJRX1JFRyhNVDYzNjBfQ0hSREVUX09WUF9FVlQpLAo+ID4+ID4gKyAgICAgTVQ2MzYw X1JFR01BUF9JUlFfUkVHKE1UNjM2MF9DSFJERVRfRVhUX0VWVCksCj4gPj4gPiArICAgICBNVDYz NjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0ZPRF9MUl9FVlQpLAo+ID4+ID4gKyAgICAgTVQ2MzYw X1JFR01BUF9JUlFfUkVHKE1UNjM2MF9GT0RfSFJfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9S RUdNQVBfSVJRX1JFRyhNVDYzNjBfRk9EX0RJU0NIR19GQUlMX0VWVCksCj4gPj4gPiArICAgICBN VDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX1VTQklEX0VWVCksCj4gPj4gPiArICAgICBNVDYz NjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0FQV0RUUlNUX0VWVCksCj4gPj4gPiArICAgICBNVDYz NjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0VOX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVH TUFQX0lSUV9SRUcoTVQ2MzYwX1FPTkJfUlNUX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVH TUFQX0lSUV9SRUcoTVQ2MzYwX01SU1RCX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQ X0lSUV9SRUcoTVQ2MzYwX09UUF9FVlQpLAo+ID4+ID4gKyAgICAgTVQ2MzYwX1JFR01BUF9JUlFf UkVHKE1UNjM2MF9WRERBT1ZfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JF RyhNVDYzNjBfU1lTVVZfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhN VDYzNjBfRkxFRF9TVFJCUElOX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lSUV9S RUcoTVQ2MzYwX0ZMRURfVE9SUElOX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBfUkVHTUFQX0lS UV9SRUcoTVQ2MzYwX0ZMRURfVFhfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJR X1JFRyhNVDYzNjBfRkxFRF9MVkZfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJR X1JFRyhNVDYzNjBfRkxFRDJfU0hPUlRfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdNQVBf SVJRX1JFRyhNVDYzNjBfRkxFRDFfU0hPUlRfRVZUKSwKPiA+PiA+ICsgICAgIE1UNjM2MF9SRUdN QVBfSVJRX1JFRyhNVDYzNjBfRkxFRDJfU1RSQl9FVlQpLAo+ID4+ID4gKyAgICAgTVQ2MzYwX1JF R01BUF9JUlFfUkVHKE1UNjM2MF9GTEVEMV9TVFJCX0VWVCksCj4gPj4gPiArICAgICBNVDYzNjBf UkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0ZMRUQyX1NUUkJfVE9fRVZUKSwKPiA+PiA+ICsgICAgIE1U NjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfRkxFRDFfU1RSQl9UT19FVlQpLAo+ID4+ID4gKyAg ICAgTVQ2MzYwX1JFR01BUF9JUlFfUkVHKE1UNjM2MF9GTEVEMl9UT1JfRVZUKSwKPiA+PiA+ICsg ICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfRkxFRDFfVE9SX0VWVCksCj4gPj4gPiAr ICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0JVQ0sxX1BHQl9FVlQpLAo+ID4+ID4g KyAgICAgTVQ2MzYwX1JFR01BUF9JUlFfUkVHKE1UNjM2MF9CVUNLMV9PQ19FVlQpLAo+ID4+ID4g KyAgICAgTVQ2MzYwX1JFR01BUF9JUlFfUkVHKE1UNjM2MF9CVUNLMV9PVl9FVlQpLAo+ID4+ID4g KyAgICAgTVQ2MzYwX1JFR01BUF9JUlFfUkVHKE1UNjM2MF9CVUNLMV9VVl9FVlQpLAo+ID4+ID4g KyAgICAgTVQ2MzYwX1JFR01BUF9JUlFfUkVHKE1UNjM2MF9CVUNLMl9QR0JfRVZUKSwKPiA+PiA+ ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfQlVDSzJfT0NfRVZUKSwKPiA+PiA+ ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfQlVDSzJfT1ZfRVZUKSwKPiA+PiA+ ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfQlVDSzJfVVZfRVZUKSwKPiA+PiA+ ICsgICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfTERPMV9PQ19FVlQpLAo+ID4+ID4g KyAgICAgTVQ2MzYwX1JFR01BUF9JUlFfUkVHKE1UNjM2MF9MRE8yX09DX0VWVCksCj4gPj4gPiAr ICAgICBNVDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0xETzNfT0NfRVZUKSwKPiA+PiA+ICsg ICAgIE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfTERPNV9PQ19FVlQpLAo+ID4+ID4gKyAg ICAgTVQ2MzYwX1JFR01BUF9JUlFfUkVHKE1UNjM2MF9MRE82X09DX0VWVCksCj4gPj4gPiArICAg ICBNVDYzNjBfUkVHTUFQX0lSUV9SRUcoTVQ2MzYwX0xETzdfT0NfRVZUKSwKPiA+PiA+ICsgICAg IE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfTERPMV9QR0JfRVZUKSwKPiA+PiA+ICsgICAg IE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfTERPMl9QR0JfRVZUKSwKPiA+PiA+ICsgICAg IE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfTERPM19QR0JfRVZUKSwKPiA+PiA+ICsgICAg IE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfTERPNV9QR0JfRVZUKSwKPiA+PiA+ICsgICAg IE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfTERPNl9QR0JfRVZUKSwKPiA+PiA+ICsgICAg IE1UNjM2MF9SRUdNQVBfSVJRX1JFRyhNVDYzNjBfTERPN19QR0JfRVZUKSwKPiA+PiA+ICt9Owo+ ID4+ID4gKwo+ID4+ID4gK3N0YXRpYyBpbnQgbXQ2MzYwX3BtdV9oYW5kbGVfcG9zdF9pcnEodm9p ZCAqaXJxX2Rydl9kYXRhKQo+ID4+ID4gK3sKPiA+PiA+ICsgICAgIHN0cnVjdCBtdDYzNjBfcG11 X2luZm8gKm1waSA9IGlycV9kcnZfZGF0YTsKPiA+PiA+ICsKPiA+PiA+ICsgICAgIHJldHVybiBy ZWdtYXBfdXBkYXRlX2JpdHMobXBpLT5yZWdtYXAsCj4gPj4gPiArICAgICAgICAgICAgIE1UNjM2 MF9QTVVfSVJRX1NFVCwgTVQ2MzYwX0lSUV9SRVRSSUcsCj4gPj4gPiBNVDYzNjBfSVJRX1JFVFJJ Ryk7Cj4gPj4gPiArfQo+ID4+ID4gKwo+ID4+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcmVnbWFw X2lycV9jaGlwIG10NjM2MF9wbXVfaXJxX2NoaXAgPSB7Cj4gPj4gPiArICAgICAuaXJxcyA9IG10 NjM2MF9wbXVfaXJxcywKPiA+PiA+ICsgICAgIC5udW1faXJxcyA9IEFSUkFZX1NJWkUobXQ2MzYw X3BtdV9pcnFzKSwKPiA+PiA+ICsgICAgIC5udW1fcmVncyA9IE1UNjM2MF9QTVVfSVJRX1JFR05V TSwKPiA+PiA+ICsgICAgIC5tYXNrX2Jhc2UgPSBNVDYzNjBfUE1VX0NIR19NQVNLMSwKPiA+PiA+ ICsgICAgIC5zdGF0dXNfYmFzZSA9IE1UNjM2MF9QTVVfQ0hHX0lSUTEsCj4gPj4gPiArICAgICAu YWNrX2Jhc2UgPSBNVDYzNjBfUE1VX0NIR19JUlExLAo+ID4+ID4gKyAgICAgLmluaXRfYWNrX21h c2tlZCA9IHRydWUsCj4gPj4gPiArICAgICAudXNlX2FjayA9IHRydWUsCj4gPj4gPiArICAgICAu aGFuZGxlX3Bvc3RfaXJxID0gbXQ2MzYwX3BtdV9oYW5kbGVfcG9zdF9pcnEsCj4gPj4gPiArfTsK PiA+PiA+ICsKPiA+PiA+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHJlZ21hcF9jb25maWcgbXQ2MzYw X3BtdV9yZWdtYXBfY29uZmlnID0gewo+ID4+ID4gKyAgICAgLnJlZ19iaXRzID0gOCwKPiA+PiA+ ICsgICAgIC52YWxfYml0cyA9IDgsCj4gPj4gPiArICAgICAubWF4X3JlZ2lzdGVyID0gTVQ2MzYw X1BNVV9NQVhSRUcsCj4gPj4gPiArfTsKPiA+PiA+ICsKPiA+PiA+ICtzdGF0aWMgY29uc3Qgc3Ry dWN0IHJlc291cmNlIG10NjM2MF9hZGNfcmVzb3VyY2VzW10gPSB7Cj4gPj4gPiArICAgICBERUZJ TkVfUkVTX0lSUV9OQU1FRChNVDYzNjBfQURDX0RPTkVJLCAiYWRjX2RvbmVpIiksCj4gPj4gPiAr fTsKPiA+PiA+ICsKPiA+PiA+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHJlc291cmNlIG10NjM2MF9j aGdfcmVzb3VyY2VzW10gPSB7Cj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYz NjBfQ0hHX1RSRUdfRVZULCAiY2hnX3RyZWdfZXZ0IiksCj4gPj4gPiArICAgICBERUZJTkVfUkVT X0lSUV9OQU1FRChNVDYzNjBfUFdSX1JEWV9FVlQsICJwd3JfcmR5X2V2dCIpLAo+ID4+ID4gKyAg ICAgREVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2MzYwX0NIR19CQVRTWVNVVl9FVlQsCj4gPj4gPiAi Y2hnX2JhdHN5c3V2X2V2dCIpLAo+ID4+ID4gKyAgICAgREVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2 MzYwX0NIR19WU1lTVVZfRVZULCAiY2hnX3ZzeXN1dl9ldnQiKSwKPiA+PiA+ICsgICAgIERFRklO RV9SRVNfSVJRX05BTUVEKE1UNjM2MF9DSEdfVlNZU09WX0VWVCwgImNoZ192c3lzb3ZfZXZ0Iiks Cj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYzNjBfQ0hHX1ZCQVRPVl9FVlQs ICJjaGdfdmJhdG92X2V2dCIpLAo+ID4+ID4gKyAgICAgREVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2 MzYwX0NIR19WQlVTT1ZfRVZULCAiY2hnX3ZidXNvdl9ldnQiKSwKPiA+PiA+ICsgICAgIERFRklO RV9SRVNfSVJRX05BTUVEKE1UNjM2MF9DSEdfQUlDQ01FQVNMLCAiY2hnX2FpY2NtZWFzbCIpLAo+ ID4+ID4gKyAgICAgREVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2MzYwX1dEVE1SSSwgIndkdG1yaSIp LAo+ID4+ID4gKyAgICAgREVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2MzYwX0NIR19SRUNIR0ksICJj aGdfcmVjaGdpIiksCj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYzNjBfQ0hH X1RFUk1JLCAiY2hnX3Rlcm1pIiksCj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChN VDYzNjBfQ0hHX0lFT0NJLCAiY2hnX2llb2NpIiksCj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lS UV9OQU1FRChNVDYzNjBfUFVNUFhfRE9ORUksICJwdW1weF9kb25laSIpLAo+ID4+ID4gKyAgICAg REVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2MzYwX0FUVEFDSF9JLCAiYXR0YWNoX2kiKSwKPiA+PiA+ ICsgICAgIERFRklORV9SRVNfSVJRX05BTUVEKE1UNjM2MF9DSFJERVRfRVhUX0VWVCwgImNocmRl dF9leHRfZXZ0IiksCj4gPj4gPiArfTsKPiA+PiA+ICsKPiA+PiA+ICtzdGF0aWMgY29uc3Qgc3Ry dWN0IHJlc291cmNlIG10NjM2MF9sZWRfcmVzb3VyY2VzW10gPSB7Cj4gPj4gPiArICAgICBERUZJ TkVfUkVTX0lSUV9OQU1FRChNVDYzNjBfRkxFRF9DSEdfVklOT1ZQX0VWVCwKPiA+PiA+ICJmbGVk X2NoZ192aW5vdnBfZXZ0IiksCj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYz NjBfRkxFRF9MVkZfRVZULCAiZmxlZF9sdmZfZXZ0IiksCj4gPj4gPiArICAgICBERUZJTkVfUkVT X0lSUV9OQU1FRChNVDYzNjBfRkxFRDJfU0hPUlRfRVZULCAiZmxlZDJfc2hvcnRfZXZ0IiksCj4g Pj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYzNjBfRkxFRDFfU0hPUlRfRVZULCAi ZmxlZDFfc2hvcnRfZXZ0IiksCj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYz NjBfRkxFRDJfU1RSQl9UT19FVlQsCj4gPj4gPiAiZmxlZDJfc3RyYl90b19ldnQiKSwKPiA+PiA+ ICsgICAgIERFRklORV9SRVNfSVJRX05BTUVEKE1UNjM2MF9GTEVEMV9TVFJCX1RPX0VWVCwKPiA+ PiA+ICJmbGVkMV9zdHJiX3RvX2V2dCIpLAo+ID4+ID4gK307Cj4gPj4gPiArCj4gPj4gPiArc3Rh dGljIGNvbnN0IHN0cnVjdCByZXNvdXJjZSBtdDYzNjBfcG1pY19yZXNvdXJjZXNbXSA9IHsKPiA+ PiA+ICsgICAgIERFRklORV9SRVNfSVJRX05BTUVEKE1UNjM2MF9CVUNLMV9QR0JfRVZULCAiYnVj azFfcGdiX2V2dCIpLAo+ID4+ID4gKyAgICAgREVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2MzYwX0JV Q0sxX09DX0VWVCwgImJ1Y2sxX29jX2V2dCIpLAo+ID4+ID4gKyAgICAgREVGSU5FX1JFU19JUlFf TkFNRUQoTVQ2MzYwX0JVQ0sxX09WX0VWVCwgImJ1Y2sxX292X2V2dCIpLAo+ID4+ID4gKyAgICAg REVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2MzYwX0JVQ0sxX1VWX0VWVCwgImJ1Y2sxX3V2X2V2dCIp LAo+ID4+ID4gKyAgICAgREVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2MzYwX0JVQ0syX1BHQl9FVlQs ICJidWNrMl9wZ2JfZXZ0IiksCj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYz NjBfQlVDSzJfT0NfRVZULCAiYnVjazJfb2NfZXZ0IiksCj4gPj4gPiArICAgICBERUZJTkVfUkVT X0lSUV9OQU1FRChNVDYzNjBfQlVDSzJfT1ZfRVZULCAiYnVjazJfb3ZfZXZ0IiksCj4gPj4gPiAr ICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYzNjBfQlVDSzJfVVZfRVZULCAiYnVjazJfdXZf ZXZ0IiksCj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYzNjBfTERPNl9PQ19F VlQsICJsZG82X29jX2V2dCIpLAo+ID4+ID4gKyAgICAgREVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2 MzYwX0xETzdfT0NfRVZULCAibGRvN19vY19ldnQiKSwKPiA+PiA+ICsgICAgIERFRklORV9SRVNf SVJRX05BTUVEKE1UNjM2MF9MRE82X1BHQl9FVlQsICJsZG82X3BnYl9ldnQiKSwKPiA+PiA+ICsg ICAgIERFRklORV9SRVNfSVJRX05BTUVEKE1UNjM2MF9MRE83X1BHQl9FVlQsICJsZG83X3BnYl9l dnQiKSwKPiA+PiA+ICt9Owo+ID4+ID4gKwo+ID4+ID4gK3N0YXRpYyBjb25zdCBzdHJ1Y3QgcmVz b3VyY2UgbXQ2MzYwX2xkb19yZXNvdXJjZXNbXSA9IHsKPiA+PiA+ICsgICAgIERFRklORV9SRVNf SVJRX05BTUVEKE1UNjM2MF9MRE8xX09DX0VWVCwgImxkbzFfb2NfZXZ0IiksCj4gPj4gPiArICAg ICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYzNjBfTERPMl9PQ19FVlQsICJsZG8yX29jX2V2dCIp LAo+ID4+ID4gKyAgICAgREVGSU5FX1JFU19JUlFfTkFNRUQoTVQ2MzYwX0xETzNfT0NfRVZULCAi bGRvM19vY19ldnQiKSwKPiA+PiA+ICsgICAgIERFRklORV9SRVNfSVJRX05BTUVEKE1UNjM2MF9M RE81X09DX0VWVCwgImxkbzVfb2NfZXZ0IiksCj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9O QU1FRChNVDYzNjBfTERPMV9QR0JfRVZULCAibGRvMV9wZ2JfZXZ0IiksCj4gPj4gPiArICAgICBE RUZJTkVfUkVTX0lSUV9OQU1FRChNVDYzNjBfTERPMl9QR0JfRVZULCAibGRvMl9wZ2JfZXZ0Iiks Cj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYzNjBfTERPM19QR0JfRVZULCAi bGRvM19wZ2JfZXZ0IiksCj4gPj4gPiArICAgICBERUZJTkVfUkVTX0lSUV9OQU1FRChNVDYzNjBf TERPNV9QR0JfRVZULCAibGRvNV9wZ2JfZXZ0IiksCj4gPj4gPiArfTsKPiA+PiA+ICsKPiA+PiA+ ICtzdGF0aWMgY29uc3Qgc3RydWN0IG1mZF9jZWxsIG10NjM2MF9kZXZzW10gPSB7Cj4gPj4gPiAr ICAgICBNVDYzNjBfTUZEX0NFTEwobXQ2MzYwX2FkYyksCj4gPj4gPiArICAgICBNVDYzNjBfTUZE X0NFTEwobXQ2MzYwX2NoZyksCj4gPj4gPiArICAgICBNVDYzNjBfTUZEX0NFTEwobXQ2MzYwX2xl ZCksCj4gPj4gPiArICAgICBNVDYzNjBfTUZEX0NFTEwobXQ2MzYwX3BtaWMpLAo+ID4+ID4gKyAg ICAgTVQ2MzYwX01GRF9DRUxMKG10NjM2MF9sZG8pLAo+ID4+ID4gKyAgICAgLyogdGNwYyBkZXYg Ki8KPiA+PiA+ICsgICAgIHsKPiA+PiA+ICsgICAgICAgICAgICAgLm5hbWUgPSAibXQ2MzYwX3Rj cGMiLAo+ID4+ID4gKyAgICAgICAgICAgICAub2ZfY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDYz NjBfdGNwYyIsCj4gPj4KPiA+PiBUaGVyZSBpcyBhIG1hY3JvIGZvciB0aGlzIHRvbyAoT0ZfTUZE X0NFTEwoKSkKPiA+Pgo+ID4KPiA+IEFDSwo+ID4KPiA+PiA+ICsgICAgIH0sCj4gPj4gPiArfTsK PiA+PiA+ICsKPiA+PiA+ICtzdGF0aWMgY29uc3QgdW5zaWduZWQgc2hvcnQgbXQ2MzYwX3NsYXZl X2FkZHJbTVQ2MzYwX1NMQVZFX01BWF0gPSB7Cj4gPj4gPiArICAgICBNVDYzNjBfUE1VX1NMQVZF SUQsCj4gPj4gPiArICAgICBNVDYzNjBfUE1JQ19TTEFWRUlELAo+ID4+ID4gKyAgICAgTVQ2MzYw X0xET19TTEFWRUlELAo+ID4+ID4gKyAgICAgTVQ2MzYwX1RDUENfU0xBVkVJRCwKPiA+PiA+ICt9 Owo+ID4+ID4gKwo+ID4+ID4gK3N0YXRpYyBpbnQgbXQ2MzYwX3BtdV9wcm9iZShzdHJ1Y3QgaTJj X2NsaWVudCAqY2xpZW50LAo+ID4+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICBjb25zdCBz dHJ1Y3QgaTJjX2RldmljZV9pZCAqaWQpCj4gPj4KPiA+PiBJZiB5b3UgdXNlIC5wcm9iZV9uZXcg KHNlZSBiZWxvdykgeW91IGNhbiBvbWl0IHRoZSAnaWQnIHBhcmFtLgo+ID4+Cj4gPgo+ID4gQUNL Cj4gPgo+ID4+ID4gK3sKPiA+PiA+ICsgICAgIHN0cnVjdCBtdDYzNjBfcG11X2luZm8gKm1waTsK PiA+Pgo+ID4+IFdlIG5vcm1hbGx5IGNhbGwgdGhpcyBkZGF0YS4KPiA+Pgo+ID4KPiA+IEFDSwo+ ID4KPiA+PiA+ICsgICAgIHVuc2lnbmVkIGludCByZWdfZGF0YSA9IDA7Cj4gPj4gPiArICAgICBp bnQgaSwgcmV0Owo+ID4+ID4gKwo+ID4+ID4gKyAgICAgbXBpID0gZGV2bV9remFsbG9jKCZjbGll bnQtPmRldiwgc2l6ZW9mKCptcGkpLCBHRlBfS0VSTkVMKTsKPiA+PiA+ICsgICAgIGlmICghbXBp KQo+ID4+ID4gKyAgICAgICAgICAgICByZXR1cm4gLUVOT01FTTsKPiA+Pgo+ID4+ICdcbicgaGVy ZS4KPiA+Pgo+ID4KPiA+IEFDSwo+ID4KPiA+PiA+ICsgICAgIG1waS0+ZGV2ID0gJmNsaWVudC0+ ZGV2Owo+ID4+ID4gKyAgICAgaTJjX3NldF9jbGllbnRkYXRhKGNsaWVudCwgbXBpKTsKPiA+PiA+ ICsKPiA+PiA+ICsgICAgIC8qIHJlZ21hcCByZWdpc2VyICovCj4gPj4KPiA+PiBUaGlzIGNvbW1l bnQgaXMgc3BlbHQgaW5jb3JyZWN0bHkgYW5kIGRvZXNuJ3QgcmVhbGx5IGFkZCBhbnl0aGluZy4K PiA+Pgo+ID4KPiA+IEFDSwo+ID4KPiA+PiA+ICsgICAgIG1waS0+cmVnbWFwID0gZGV2bV9yZWdt YXBfaW5pdF9pMmMoY2xpZW50LAo+ID4+ID4gJm10NjM2MF9wbXVfcmVnbWFwX2NvbmZpZyk7Cj4g Pj4gPiArICAgICBpZiAoSVNfRVJSKG1waS0+cmVnbWFwKSkgewo+ID4+ID4gKyAgICAgICAgICAg ICBkZXZfZXJyKCZjbGllbnQtPmRldiwgInJlZ21hcCByZWdpc3RlciBmYWlsXG4iKTsKPiA+Pgo+ ID4+ICJGYWlsZWQgdG8gcmVnaXN0ZXIgcmVnbWFwIgo+ID4+Cj4gPgo+ID4gQUNLCj4gPgo+ID4+ ID4gKyAgICAgICAgICAgICByZXR1cm4gUFRSX0VSUihtcGktPnJlZ21hcCk7Cj4gPj4gPiArICAg ICB9Cj4gPj4KPiA+PiAnXG4nIGhlcmUuCj4gPj4KPiA+Cj4gPiBBQ0sKPiA+Cj4gPj4gPiArICAg ICAvKiBjaGlwIGlkIGNoZWNrICovCj4gPj4KPiA+PiBBZ2FpbiwgdGhlIGNvZGUgaXMgcHJldHR5 IG9idmlvdXMuCj4gPj4KPiA+Cj4gPiBBQ0sKPiA+Cj4gPj4gPiArICAgICByZXQgPSByZWdtYXBf cmVhZChtcGktPnJlZ21hcCwgTVQ2MzYwX1BNVV9ERVZfSU5GTywgJnJlZ19kYXRhKTsKPiA+PiA+ ICsgICAgIGlmIChyZXQgPCAwKSB7Cj4gPj4gPiArICAgICAgICAgICAgIGRldl9lcnIoJmNsaWVu dC0+ZGV2LCAiZGV2aWNlIG5vdCBmb3VuZFxuIik7Cj4gPj4KPiA+PiAiRGV2aWNlIG5vdCBmb3Vu ZCIKPiA+Pgo+ID4KPiA+IEFDSwo+ID4KPiA+PiA+ICsgICAgICAgICAgICAgcmV0dXJuIHJldDsK PiA+PiA+ICsgICAgIH0KPiA+Pgo+ID4+ICdcbicgaGVyZS4KPiA+Pgo+ID4KPiA+IEFDSwo+ID4K PiA+PiA+ICsgICAgIGlmICgocmVnX2RhdGEgJiBDSElQX1ZFTl9NQVNLKSAhPSBDSElQX1ZFTl9N VDYzNjApIHsKPiA+PiA+ICsgICAgICAgICAgICAgZGV2X2VycigmY2xpZW50LT5kZXYsICJub3Qg bXQ2MzYwIGNoaXBcbiIpOwo+ID4+Cj4gPj4gIkRldmljZSBub3Qgc3VwcG9ydGVkIgo+ID4+Cj4g Pgo+ID4gQUNLCj4gPgo+ID4+ID4gKyAgICAgICAgICAgICByZXR1cm4gLUVOT0RFVjsKPiA+PiA+ ICsgICAgIH0KPiA+Pgo+ID4+ICdcbicgaGVyZS4KPiA+Pgo+ID4KPiA+IEFDSwo+ID4KPiA+PiA+ ICsgICAgIG1waS0+Y2hpcF9yZXYgPSByZWdfZGF0YSAmIENISVBfUkVWX01BU0s7Cj4gPj4KPiA+ PiBEbyB0aGlzIGFib3ZlIHRoZSBjaGVjaywgdGhlbiBkbwo+ID4+Cj4gPj4gICAobXBpLT5jaGlw X3JldiAhPSBDSElQX1ZFTl9NVDYzNjApCj4gPj4KPiA+PiAuLi4gYWJvdmUuCj4gPj4KPiA+Cj4g PiBBQ0sKPiA+Cj4gPj4gPiArICAgICAvKiBpcnEgcmVnaXN0ZXIgKi8KPiA+Pgo+ID4+IFBsZWFz ZSByZW1vdmUgYWxsIG9mIHRoZXNlIGNvbW1lbnRzLgo+ID4+Cj4gPgo+ID4gQUNLCj4gPgo+ID4+ ID4gKyAgICAgbWVtY3B5KCZtcGktPmlycV9jaGlwLCAmbXQ2MzYwX3BtdV9pcnFfY2hpcCwKPiA+ PiA+IHNpemVvZihtcGktPmlycV9jaGlwKSk7Cj4gPj4KPiA+PiBXaHkgZG8gd2UgbmVlZCB0byBt YWtlIGEgY29weSBvZiBpdD8KPiA+Pgo+ID4KPiA+IGNvbnNpZGVyIG9mIHVzaW5nIG11dGlwbGUg bXQ2MzYwIGNoaXBzLCB3ZSBjYW4gc2VwZXJhdGUgZGlmZiBpMmMKPiA+IGlycV9jaGlwLm5hbWUg YnkgZGV2aWNlX25hbWUgb3JpZ2luYWxseQo+ID4gYnV0IHdlIGNhbid0IGZpbmQgc2lsaW1hciBj YXNlIGJ5IG92ZXJ2aWV3IG90aGVyIG1mZCBkcml2ZXIKPiA+IHdlIHdpbGwgZGVsZXRlIHRoaXMK PiA+Cj4gPj4gPiArICAgICBtcGktPmlycV9jaGlwLm5hbWUgPSBkZXZfbmFtZSgmY2xpZW50LT5k ZXYpOwo+ID4+Cj4gPj4gV2UgYWxyZWFkeSBrbm93IHRoZSBuYW1lLiAgV2h5IGRvIHdlIG5lZWQg dG8gZG8gdGhpcyBkeW5hbWljYWxseT8KPiA+Pgo+ID4KPiA+IHNhbWUgYXMgYWJvdmUKPiA+Cj4g Pj4gPiArICAgICBtcGktPmlycV9jaGlwLmlycV9kcnZfZGF0YSA9IG1waTsKPiA+Pgo+ID4+IFdl IGFscmVhZHkgc2F2ZWQgZGRhdGEuICBXaHkgZG8gd2UgbmVlZCB0byBzYXZlIGl0IGhlcmUgYXMg d2VsbD8KPiA+Pgo+ID4KPiA+IHdlIGltcGxlbWVudCBvcHMgIi5oYW5kbGVfcG9zdF9pcnEiIGZv ciBpcnEgcmV0cmlnZ2VyIHdoZW4gaXJxIHN0dWNrIGtlZXAKPiA+IGxvdwo+ID4KPiA+PiA+ICsg ICAgIHJldCA9IGRldm1fcmVnbWFwX2FkZF9pcnFfY2hpcCgmY2xpZW50LT5kZXYsIG1waS0+cmVn bWFwLAo+ID4+ID4gY2xpZW50LT5pcnEsCj4gPj4gPiArICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgSVJRRl9UUklHR0VSX0ZBTExJTkcsIDAsCj4gPj4gPiAmbXBpLT5pcnFfY2hp cCwKPiA+PiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAmbXBpLT5pcnFf ZGF0YSk7Cj4gPj4gPiArICAgICBpZiAocmV0IDwgMCkgewo+ID4+Cj4gPj4gSXMgKHJldCA+IDAp IHZhbGlkPwo+ID4+Cj4gPgo+ID4gd2UgY29uc2lkZXIgbXQ2MzYwIGRyaXZlciBuZWVkIGFkZCBp cnFfY2hpcCBmb3IgZnVsbCBmdW5jdGlvbmFsaXR5Cj4gPgo+ID4+ID4gKyAgICAgICAgICAgICBk ZXZfZXJyKCZjbGllbnQtPmRldiwgInJlZ21hcCBpcnEgY2hpcCBhZGQgZmFpbFxuIik7Cj4gPj4K PiA+PiAiRmFpbGVkIHRvIGFkZCBSZWdtYXAgSVJRIENoaXAiCj4gPj4KPiA+Cj4gPiBBQ0sKPiA+ Cj4gPj4gPiArICAgICAgICAgICAgIHJldHVybiByZXQ7Cj4gPj4gPiArICAgICB9Cj4gPj4KPiA+ PiAnXG4nIGhlcmUuCj4gPj4KPiA+Cj4gPiBBQ0sKPiA+Cj4gPj4gPiArICAgICAvKiBuZXcgaTJj IHNsYXZlIGRldmljZSAqLwo+ID4+ID4gKyAgICAgZm9yIChpID0gMDsgaSA8IE1UNjM2MF9TTEFW RV9NQVg7IGkrKykgewo+ID4+ID4gKyAgICAgICAgICAgICBpZiAobXQ2MzYwX3NsYXZlX2FkZHJb aV0gPT0gY2xpZW50LT5hZGRyKSB7Cj4gPj4gPiArICAgICAgICAgICAgICAgICAgICAgbXBpLT5p MmNbaV0gPSBjbGllbnQ7Cj4gPj4gPiArICAgICAgICAgICAgICAgICAgICAgY29udGludWU7Cj4g Pj4gPiArICAgICAgICAgICAgIH0KPiA+PiA+ICsgICAgICAgICAgICAgbXBpLT5pMmNbaV0gPSBp MmNfbmV3X2R1bW15KGNsaWVudC0+YWRhcHRlciwKPiA+PiA+ICsgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIG10NjM2MF9zbGF2ZV9hZGRyW2ldKTsKPiA+PiA+ICsgICAg ICAgICAgICAgaWYgKCFtcGktPmkyY1tpXSkgewo+ID4+ID4gKyAgICAgICAgICAgICAgICAgICAg IGRldl9lcnIoJmNsaWVudC0+ZGV2LCAibmV3IGkyYyBkZXYgWyVkXSBmYWlsXG4iLAo+ID4+ID4g aSk7Cj4gPj4gPiArICAgICAgICAgICAgICAgICAgICAgcmV0ID0gLUVOT0RFVjsKPiA+PiA+ICsg ICAgICAgICAgICAgICAgICAgICBnb3RvIG91dDsKPiA+PiA+ICsgICAgICAgICAgICAgfQo+ID4+ ID4gKyAgICAgICAgICAgICBpMmNfc2V0X2NsaWVudGRhdGEobXBpLT5pMmNbaV0sIG1waSk7Cj4g Pj4gPiArICAgICB9Cj4gPj4KPiA+PiBUaGlzIGRvZXNuJ3QgbG9vayByaWdodCB0byBtZS4KPiA+ Pgo+ID4+IFdvbGZyYW0sIHdvdWxkIHlvdSBiZSBraW5kIGVub3VnaCB0byB0YWtlIGEgbG9vaz8K PiA+Pgo+ID4+ICdcbicgaGVyZS4KPiA+Pgo+ID4KPiA+IEFDSwo+ID4KPiA+PiA+ICsgICAgIC8q IG1mZCBjZWxsIHJlZ2lzdGVyICovCj4gPj4gPiArICAgICByZXQgPSBkZXZtX21mZF9hZGRfZGV2 aWNlcygmY2xpZW50LT5kZXYsIFBMQVRGT1JNX0RFVklEX0FVVE8sCj4gPj4gPiArICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICBtdDYzNjBfZGV2cywgQVJSQVlfU0laRShtdDYzNjBfZGV2 cyksCj4gPj4gPiBOVUxMLAo+ID4+ID4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg MCwKPiA+PiA+IHJlZ21hcF9pcnFfZ2V0X2RvbWFpbihtcGktPmlycV9kYXRhKSk7Cj4gPj4gPiAr ICAgICBpZiAocmV0IDwgMCkgewo+ID4+ID4gKyAgICAgICAgICAgICBkZXZfZXJyKCZjbGllbnQt PmRldiwgIm1mZCBhZGQgY2VsbHMgZmFpbFxuIik7Cj4gPj4gPiArICAgICAgICAgICAgIGdvdG8g b3V0Owo+ID4+ID4gKyAgICAgfQo+ID4+Cj4gPj4gJ1xuJyBoZXJlLgo+ID4+Cj4gPgo+ID4gQUNL Cj4gPgo+ID4+ID4gKyAgICAgZGV2X2luZm8oJmNsaWVudC0+ZGV2LCAiU3VjY2Vzc2Z1bGx5IHBy b2JlZFxuIik7Cj4gPj4KPiA+PiBQbGVhc2UgcmVtb3ZlIHRoaXMgbGluZS4gIEl0IGRvZXNuJ3Qg cHJvdmlkZSBhbnl0aGluZy4KPiA+Pgo+ID4KPiA+IEFDSwo+ID4KPiA+PiA+ICsgICAgIHJldHVy biAwOwo+ID4+ID4gK291dDoKPiA+PiA+ICsgICAgIHdoaWxlICgtLWkgPj0gMCkgewo+ID4+ID4g KyAgICAgICAgICAgICBpZiAobXBpLT5pMmNbaV0tPmFkZHIgPT0gY2xpZW50LT5hZGRyKQo+ID4+ ID4gKyAgICAgICAgICAgICAgICAgICAgIGNvbnRpbnVlOwo+ID4+ID4gKyAgICAgICAgICAgICBp MmNfdW5yZWdpc3Rlcl9kZXZpY2UobXBpLT5pMmNbaV0pOwo+ID4+ID4gKyAgICAgfQo+ID4+Cj4g Pj4gJ1xuJyBoZXJlLgo+ID4+Cj4gPgo+ID4gQUNLCj4gPgo+ID4+ID4gKyAgICAgcmV0dXJuIHJl dDsKPiA+PiA+ICt9Cj4gPj4gPiArCj4gPj4gPiArc3RhdGljIGludCBtdDYzNjBfcG11X3JlbW92 ZShzdHJ1Y3QgaTJjX2NsaWVudCAqY2xpZW50KQo+ID4+ID4gK3sKPiA+PiA+ICsgICAgIHN0cnVj dCBtdDYzNjBfcG11X2luZm8gKm1waSA9IGkyY19nZXRfY2xpZW50ZGF0YShjbGllbnQpOwo+ID4+ ID4gKyAgICAgaW50IGk7Cj4gPj4gPiArCj4gPj4gPiArICAgICBmb3IgKGkgPSAwOyBpIDwgTVQ2 MzYwX1NMQVZFX01BWDsgaSsrKSB7Cj4gPj4gPiArICAgICAgICAgICAgIGlmIChtcGktPmkyY1tp XS0+YWRkciA9PSBjbGllbnQtPmFkZHIpCj4gPj4gPiArICAgICAgICAgICAgICAgICAgICAgY29u dGludWU7Cj4gPj4gPiArICAgICAgICAgICAgIGkyY191bnJlZ2lzdGVyX2RldmljZShtcGktPmky Y1tpXSk7Cj4gPj4gPiArICAgICB9Cj4gPj4KPiA+PiAnXG4nIGhlcmUuCj4gPj4KPiA+Cj4gPiBB Q0sKPiA+Cj4gPj4gPiArICAgICByZXR1cm4gMDsKPiA+PiA+ICt9Cj4gPj4gPiArCj4gPj4gPiAr c3RhdGljIGludCBfX21heWJlX3VudXNlZCBtdDYzNjBfcG11X3N1c3BlbmQoc3RydWN0IGRldmlj ZSAqZGV2KQo+ID4+ID4gK3sKPiA+PiA+ICsgICAgIHN0cnVjdCBpMmNfY2xpZW50ICppMmMgPSB0 b19pMmNfY2xpZW50KGRldik7Cj4gPj4gPiArCj4gPj4gPiArICAgICBpZiAoZGV2aWNlX21heV93 YWtldXAoZGV2KSkKPiA+PiA+ICsgICAgICAgICAgICAgZW5hYmxlX2lycV93YWtlKGkyYy0+aXJx KTsKPiA+Pgo+ID4+ICdcbicgaGVyZS4KPiA+Pgo+ID4KPiA+IEFDSwo+ID4KPiA+PiA+ICsgICAg IHJldHVybiAwOwo+ID4+ID4gK30KPiA+PiA+ICsKPiA+PiA+ICtzdGF0aWMgaW50IF9fbWF5YmVf dW51c2VkIG10NjM2MF9wbXVfcmVzdW1lKHN0cnVjdCBkZXZpY2UgKmRldikKPiA+PiA+ICt7Cj4g Pj4gPiArCj4gPj4gPiArICAgICBzdHJ1Y3QgaTJjX2NsaWVudCAqaTJjID0gdG9faTJjX2NsaWVu dChkZXYpOwo+ID4+ID4gKwo+ID4+ID4gKyAgICAgaWYgKGRldmljZV9tYXlfd2FrZXVwKGRldikp Cj4gPj4gPiArICAgICAgICAgICAgIGRpc2FibGVfaXJxX3dha2UoaTJjLT5pcnEpOwo+ID4+Cj4g Pj4gJ1xuJyBoZXJlLgo+ID4+Cj4gPgo+ID4gQUNLCj4gPgo+ID4+ID4gKyAgICAgcmV0dXJuIDA7 Cj4gPj4gPiArfQo+ID4+ID4gKwo+ID4+ID4gK3N0YXRpYyBTSU1QTEVfREVWX1BNX09QUyhtdDYz NjBfcG11X3BtX29wcywKPiA+PiA+ICsgICAgICAgICAgICAgICAgICAgICAgbXQ2MzYwX3BtdV9z dXNwZW5kLCBtdDYzNjBfcG11X3Jlc3VtZSk7Cj4gPj4gPiArCj4gPj4gPiArc3RhdGljIGNvbnN0 IHN0cnVjdCBvZl9kZXZpY2VfaWQgX19tYXliZV91bnVzZWQgbXQ2MzYwX3BtdV9vZl9pZFtdID0g ewo+ID4+ID4gKyAgICAgeyAuY29tcGF0aWJsZSA9ICJtZWRpYXRlayxtdDYzNjBfcG11IiwgfSwK PiA+PiA+ICsgICAgIHt9LAo+ID4+ID4gK307Cj4gPj4gPiArTU9EVUxFX0RFVklDRV9UQUJMRShv ZiwgbXQ2MzYwX3BtdV9vZl9pZCk7Cj4gPj4gPiArCj4gPj4gPiArc3RhdGljIGNvbnN0IHN0cnVj dCBpMmNfZGV2aWNlX2lkIG10NjM2MF9wbXVfaWRbXSA9IHsKPiA+PiA+ICsgICAgIHsgIm10NjM2 MF9wbXUiLCAwIH0sCj4gPj4gPiArICAgICB7fSwKPiA+PiA+ICt9Owo+ID4+ID4gK01PRFVMRV9E RVZJQ0VfVEFCTEUoaTJjLCBtdDYzNjBfcG11X2lkKTsKPiA+Pgo+ID4+IElmIHlvdSB1c2UgLnBy b2JlX25ldyAoc2VlIGJlbG93LCB5b3UgY2FuIHJlbW92ZSB0aGlzIHRhYmxlLgo+ID4+Cj4gPgo+ ID4gQUNLCj4gPgo+ID4+ID4gK3N0YXRpYyBzdHJ1Y3QgaTJjX2RyaXZlciBtdDYzNjBfcG11X2Ry aXZlciA9IHsKPiA+PiA+ICsgICAgIC5kcml2ZXIgPSB7Cj4gPj4gPiArICAgICAgICAgICAgIC5u YW1lID0gIm10NjM2MF9wbXUiLAo+ID4+ID4gKyAgICAgICAgICAgICAub3duZXIgPSBUSElTX01P RFVMRSwKPiA+Pgo+ID4+IFRoaXMgaXMgbm8gbG9uZ2VyIHJlcXVpcmVkLgo+ID4+Cj4gPgo+ID4g QUNLCj4gPgo+ID4+ID4gKyAgICAgICAgICAgICAucG0gPSAmbXQ2MzYwX3BtdV9wbV9vcHMsCj4g Pj4gPiArICAgICAgICAgICAgIC5vZl9tYXRjaF90YWJsZSA9IG9mX21hdGNoX3B0cihtdDYzNjBf cG11X29mX2lkKSwKPiA+PiA+ICsgICAgIH0sCj4gPj4gPiArICAgICAucHJvYmUgPSBtdDYzNjBf cG11X3Byb2JlLAo+ID4+Cj4gPj4gVXNlIC5wcm9iZV9uZXcgaGVyZS4KPiA+Pgo+ID4KPiA+IEFD Swo+ID4KPiA+PiA+ICsgICAgIC5yZW1vdmUgPSBtdDYzNjBfcG11X3JlbW92ZSwKPiA+PiA+ICsg ICAgIC5pZF90YWJsZSA9IG10NjM2MF9wbXVfaWQsCj4gPj4gPiArfTsKPiA+PiA+ICttb2R1bGVf aTJjX2RyaXZlcihtdDYzNjBfcG11X2RyaXZlcik7Cj4gPj4gPiArCj4gPj4gPiArTU9EVUxFX0FV VEhPUigiQ1lfSHVhbmcgPGN5X2h1YW5nQHJpY2h0ZWsuY29tPiIpOwo+ID4+ID4gK01PRFVMRV9E RVNDUklQVElPTigiTVQ2MzYwIFBNVSBJMkMgRHJpdmVyIik7Cj4gPj4gPiArTU9EVUxFX0xJQ0VO U0UoIkdQTCIpOwo+ID4+ID4gK01PRFVMRV9WRVJTSU9OKCIxLjAuMCIpOwo+ID4+ID4gZGlmZiAt LWdpdCBhL2luY2x1ZGUvbGludXgvbWZkL210NjM2MC1wcml2YXRlLmgKPiA+PiA+IGIvaW5jbHVk ZS9saW51eC9tZmQvbXQ2MzYwLXByaXZhdGUuaAo+ID4+ID4gbmV3IGZpbGUgbW9kZSAxMDA2NDQK PiA+PiA+IGluZGV4IDAwMDAwMDAuLmIwN2IzZDkKPiA+PiA+IC0tLSAvZGV2L251bGwKPiA+PiA+ ICsrKyBiL2luY2x1ZGUvbGludXgvbWZkL210NjM2MC1wcml2YXRlLmgKPiA+Pgo+ID4+IFdoeSBk byB5b3UgbmVlZCAyIGhlYWRlciBmaWxlcz8KPiA+Pgo+ID4KPiA+IEFjY29yZGluZyB0byBvdXIg YXJjaGl0ZWN0dXJlIGFzIGF0dGFjaG1lbnQsCj4gPiBtdDYzNjAgaGF2ZSA0IGkyYyBzbGF2ZSBh ZGRyZXNzIGZvciBkaWZmZXJlbnQgcGFydHMKPiA+IHNvIHdlIHNldCB3aG9sZSByZWdpc3RlciB0 YWJsZSBpbiBtdDYzNjAtcHJpdmF0ZS5oLCBpdCB3aWxsIGJlCj4gPiBpbmNsdWRlZCBieSBvdGhl ciBtb2R1bGVzCj4gPiB3ZSB3aWxsIGRlbGV0ZSBpdCBuZXh0IHBhdGNoCj4gPiBhbmQgd2Ugd2ls bCBhZGQgdW50aWwgd2UgdXNlIGl0Cj4gPgo+ID4+ID4gQEAgLTAsMCArMSwyNzkgQEAKPiA+PiA+ ICsvKiBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogR1BMLTIuMCAqLwo+ID4+ID4gKy8qCj4gPj4g PiArICogQ29weXJpZ2h0IChjKSAyMDE5IE1lZGlhVGVrIEluYy4KPiA+PiA+ICsgKi8KPiA+PiA+ ICsKPiA+PiA+ICsjaWZuZGVmIF9fTVQ2MzYwX1BSSVZBVEVfSF9fCj4gPj4gPiArI2RlZmluZSBf X01UNjM2MF9QUklWQVRFX0hfXwo+ID4+Cj4gPj4gX19NRkRfTVQ2MzYwX0hfXwo+ID4+Cj4gPj4g PiArI2luY2x1ZGUgPGxpbnV4L2ludGVycnVwdC5oPgo+ID4+ID4gKwo+ID4+ID4gKy8qIFBNVSBy ZWdpc3RlciBkZWZpbmluaXRpb24gKi8KPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfREVWX0lO Rk8gICAgICAgICAgICAgICAgICAoMHgwMCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ09S RV9DVFJMMSAgICAgICAgICAgICAgICAgICAgICAgICgweDAxKQo+ID4+ID4gKyNkZWZpbmUgTVQ2 MzYwX1BNVV9SU1QxICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgKDB4MDIpCj4gPj4gPiAr I2RlZmluZSBNVDYzNjBfUE1VX0NSQ0VOICAgICAgICAgICAgICAgICAgICAgKDB4MDMpCj4gPj4g PiArI2RlZmluZSBNVDYzNjBfUE1VX1JTVF9QQVNfQ09ERTEgICAgICAgICAgICAgKDB4MDQpCj4g Pj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JTVF9QQVNfQ09ERTIgICAgICAgICAgICAgKDB4MDUp Cj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NPUkVfQ1RSTDIgICAgICAgICAgICAgICAgICAg ICAgICAoMHgwNikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfVE1fUEFTX0NPREUxICAgICAg ICAgICAgICAgICAgICAgICgweDA3KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9UTV9QQVNf Q09ERTIgICAgICAgICAgICAgICAgICAgICAgKDB4MDgpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBf UE1VX1RNX1BBU19DT0RFMyAgICAgICAgICAgICAgICAgICAgICAoMHgwOSkKPiA+PiA+ICsjZGVm aW5lIE1UNjM2MF9QTVVfVE1fUEFTX0NPREU0ICAgICAgICAgICAgICAgICAgICAgICgweDBBKQo+ ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9JUlFfSU5EICAgICAgICAgICAgICAgICAgICgweDBC KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9JUlFfTUFTSyAgICAgICAgICAgICAgICAgICgw eDBDKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9JUlFfU0VUICAgICAgICAgICAgICAgICAg ICgweDBEKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9TSEROX0NUUkwgICAgICAgICAgICAg ICAgICgweDBFKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9UTV9JTkYgICAgICAgICAgICAg ICAgICAgICgweDBGKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9JMkNfQ1RSTCAgICAgICAg ICAgICAgICAgICgweDEwKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9DSEdfQ1RSTDEgICAg ICAgICAgICAgICAgICgweDExKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9DSEdfQ1RSTDIg ICAgICAgICAgICAgICAgICgweDEyKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9DSEdfQ1RS TDMgICAgICAgICAgICAgICAgICgweDEzKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9DSEdf Q1RSTDQgICAgICAgICAgICAgICAgICgweDE0KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9D SEdfQ1RSTDUgICAgICAgICAgICAgICAgICgweDE1KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BN VV9DSEdfQ1RSTDYgICAgICAgICAgICAgICAgICgweDE2KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYw X1BNVV9DSEdfQ1RSTDcgICAgICAgICAgICAgICAgICgweDE3KQo+ID4+ID4gKyNkZWZpbmUgTVQ2 MzYwX1BNVV9DSEdfQ1RSTDggICAgICAgICAgICAgICAgICgweDE4KQo+ID4+ID4gKyNkZWZpbmUg TVQ2MzYwX1BNVV9DSEdfQ1RSTDkgICAgICAgICAgICAgICAgICgweDE5KQo+ID4+ID4gKyNkZWZp bmUgTVQ2MzYwX1BNVV9DSEdfQ1RSTDEwICAgICAgICAgICAgICAgICAgICAgICAgKDB4MUEpCj4g Pj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NIR19DVFJMMTEgICAgICAgICAgICAgICAgICAgICAg ICAoMHgxQikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0NUUkwxMiAgICAgICAgICAg ICAgICAgICAgICAgICgweDFDKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9DSEdfQ1RSTDEz ICAgICAgICAgICAgICAgICAgICAgICAgKDB4MUQpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1V X0NIR19DVFJMMTQgICAgICAgICAgICAgICAgICAgICAgICAoMHgxRSkKPiA+PiA+ICsjZGVmaW5l IE1UNjM2MF9QTVVfQ0hHX0NUUkwxNSAgICAgICAgICAgICAgICAgICAgICAgICgweDFGKQo+ID4+ ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9DSEdfQ1RSTDE2ICAgICAgICAgICAgICAgICAgICAgICAg KDB4MjApCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NIR19BSUNDX1JFU1VMVCAgICAgICAg ICAgKDB4MjEpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0RFVklDRV9UWVBFICAgICAgICAg ICAgICAgICAgICAgICAoMHgyMikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfUUNfQ09OVFJP TDEgICAgICAgICAgICAgICAgICAgICAgICgweDIzKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BN VV9RQ19DT05UUk9MMiAgICAgICAgICAgICAgICAgICAgICAgKDB4MjQpCj4gPj4gPiArI2RlZmlu ZSBNVDYzNjBfUE1VX1FDMzBfQ09OVFJPTDEgICAgICAgICAgICAgKDB4MjUpCj4gPj4gPiArI2Rl ZmluZSBNVDYzNjBfUE1VX1FDMzBfQ09OVFJPTDIgICAgICAgICAgICAgKDB4MjYpCj4gPj4gPiAr I2RlZmluZSBNVDYzNjBfUE1VX1VTQl9TVEFUVVMxICAgICAgICAgICAgICAgICAgICAgICAoMHgy NykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfUUNfU1RBVFVTMSAgICAgICAgICAgICAgICAg ICAgICAgICgweDI4KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9RQ19TVEFUVVMyICAgICAg ICAgICAgICAgICAgICAgICAgKDB4MjkpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NIR19Q VU1QICAgICAgICAgICAgICAgICAgKDB4MkEpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NI R19DVFJMMTcgICAgICAgICAgICAgICAgICAgICAgICAoMHgyQikKPiA+PiA+ICsjZGVmaW5lIE1U NjM2MF9QTVVfQ0hHX0NUUkwxOCAgICAgICAgICAgICAgICAgICAgICAgICgweDJDKQo+ID4+ID4g KyNkZWZpbmUgTVQ2MzYwX1BNVV9DSFJERVRfQ1RSTDEgICAgICAgICAgICAgICAgICAgICAgKDB4 MkQpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NIUkRFVF9DVFJMMiAgICAgICAgICAgICAg ICAgICAgICAoMHgyRSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfRFBETl9DVFJMICAgICAg ICAgICAgICAgICAoMHgyRikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9D VFJMMSAgICAgICAgICAoMHgzMCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERF Tl9DVFJMMiAgICAgICAgICAoMHgzMSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJ RERFTl9DVFJMMyAgICAgICAgICAoMHgzMikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hH X0hJRERFTl9DVFJMNCAgICAgICAgICAoMHgzMykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVf Q0hHX0hJRERFTl9DVFJMNSAgICAgICAgICAoMHgzNCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9Q TVVfQ0hHX0hJRERFTl9DVFJMNiAgICAgICAgICAoMHgzNSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2 MF9QTVVfQ0hHX0hJRERFTl9DVFJMNyAgICAgICAgICAoMHgzNikKPiA+PiA+ICsjZGVmaW5lIE1U NjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMOCAgICAgICAgICAoMHgzNykKPiA+PiA+ICsjZGVmaW5l IE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMOSAgICAgICAgICAoMHgzOCkKPiA+PiA+ICsjZGVm aW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMMTAgICAgICAgICAoMHgzOSkKPiA+PiA+ICsj ZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMMTEgICAgICAgICAoMHgzQSkKPiA+PiA+ ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMMTIgICAgICAgICAoMHgzQikKPiA+ PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMMTMgICAgICAgICAoMHgzQykK PiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMMTQgICAgICAgICAoMHgz RCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMMTUgICAgICAgICAo MHgzRSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMMTYgICAgICAg ICAoMHgzRikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMMTcgICAg ICAgICAoMHg0MCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJMMTgg ICAgICAgICAoMHg0MSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9DVFJM MTkgICAgICAgICAoMHg0MikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERFTl9D VFJMMjAgICAgICAgICAoMHg0MykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJRERF Tl9DVFJMMjEgICAgICAgICAoMHg0NCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX0hJ RERFTl9DVFJMMjIgICAgICAgICAoMHg0NSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hH X0hJRERFTl9DVFJMMjMgICAgICAgICAoMHg0NikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVf Q0hHX0hJRERFTl9DVFJMMjQgICAgICAgICAoMHg0NykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9Q TVVfQ0hHX0hJRERFTl9DVFJMMjUgICAgICAgICAoMHg0OCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2 MF9QTVVfQkMxMl9DVFJMICAgICAgICAgICAgICAgICAoMHg0OSkKPiA+PiA+ICsjZGVmaW5lIE1U NjM2MF9QTVVfQ0hHX1NUQVQgICAgICAgICAgICAgICAgICAoMHg0QSkKPiA+PiA+ICsjZGVmaW5l IE1UNjM2MF9QTVVfUkVTVjEgICAgICAgICAgICAgICAgICAgICAoMHg0QikKPiA+PiA+ICsjZGVm aW5lIE1UNjM2MF9QTVVfVFlQRUNfT1RQX1RIX1NFTF9DT0RFSCAgICAoMHg0RSkKPiA+PiA+ICsj ZGVmaW5lIE1UNjM2MF9QTVVfVFlQRUNfT1RQX1RIX1NFTF9DT0RFTCAgICAoMHg0RikKPiA+PiA+ ICsjZGVmaW5lIE1UNjM2MF9QTVVfVFlQRUNfT1RQX0hZU1RfVEggICAgICAgICAoMHg1MCkKPiA+ PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfVFlQRUNfT1RQX0NUUkwgICAgICAgICAgICAoMHg1MSkK PiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQURDX0JBVF9EQVRBX0ggICAgICAgICAgICAoMHg1 MikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQURDX0JBVF9EQVRBX0wgICAgICAgICAgICAo MHg1MykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfSU1JRF9CQUNLQlNUX09OICAgICAgICAg ICAoMHg1NCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfSU1JRF9CQUNLQlNUX09GRiAgICAg ICAgICAoMHg1NSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQURDX0NPTkZJRyAgICAgICAg ICAgICAgICAgICAgICAgICgweDU2KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9BRENfRU4y ICAgICAgICAgICAgICAgICAgICgweDU3KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9BRENf SURMRV9UICAgICAgICAgICAgICAgICAgICAgICAgKDB4NTgpCj4gPj4gPiArI2RlZmluZSBNVDYz NjBfUE1VX0FEQ19SUFRfMSAgICAgICAgICAgICAgICAgKDB4NUEpCj4gPj4gPiArI2RlZmluZSBN VDYzNjBfUE1VX0FEQ19SUFRfMiAgICAgICAgICAgICAgICAgKDB4NUIpCj4gPj4gPiArI2RlZmlu ZSBNVDYzNjBfUE1VX0FEQ19SUFRfMyAgICAgICAgICAgICAgICAgKDB4NUMpCj4gPj4gPiArI2Rl ZmluZSBNVDYzNjBfUE1VX0FEQ19SUFRfT1JHMSAgICAgICAgICAgICAgICAgICAgICAoMHg1RCkK PiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQURDX1JQVF9PUkcyICAgICAgICAgICAgICAgICAg ICAgICgweDVFKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9CQVRfT1ZQX1RIX1NFTF9DT0RF SCAgICAgICAgICAgICAgKDB4NUYpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0JBVF9PVlBf VEhfU0VMX0NPREVMICAgICAgICAgICAgICAoMHg2MCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9Q TVVfQ0hHX0NUUkwxOSAgICAgICAgICAgICAgICAgICAgICAgICgweDYxKQo+ID4+ID4gKyNkZWZp bmUgTVQ2MzYwX1BNVV9WRERBU1VQUExZICAgICAgICAgICAgICAgICAgICAgICAgKDB4NjIpCj4g Pj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0JDMTJfTUFOVUFMICAgICAgICAgICAgICAgICAgICAg ICAoMHg2MykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHREVUX0ZVTkMgICAgICAgICAg ICAgICAgICAgICAgICgweDY0KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9GT0RfQ1RSTCAg ICAgICAgICAgICAgICAgICgweDY1KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9DSEdfQ1RS TDIwICAgICAgICAgICAgICAgICAgICAgICAgKDB4NjYpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBf UE1VX0NIR19ISURERU5fQ1RSTDI2ICAgICAgICAgKDB4NjcpCj4gPj4gPiArI2RlZmluZSBNVDYz NjBfUE1VX0NIR19ISURERU5fQ1RSTDI3ICAgICAgICAgKDB4NjgpCj4gPj4gPiArI2RlZmluZSBN VDYzNjBfUE1VX1JFU1YyICAgICAgICAgICAgICAgICAgICAgKDB4NjkpCj4gPj4gPiArI2RlZmlu ZSBNVDYzNjBfUE1VX1VTQklEX0NUUkwxICAgICAgICAgICAgICAgICAgICAgICAoMHg2RCkKPiA+ PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfVVNCSURfQ1RSTDIgICAgICAgICAgICAgICAgICAgICAg ICgweDZFKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9VU0JJRF9DVFJMMyAgICAgICAgICAg ICAgICAgICAgICAgKDB4NkYpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0ZMRURfQ0ZHICAg ICAgICAgICAgICAgICAgKDB4NzApCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JFU1YzICAg ICAgICAgICAgICAgICAgICAgKDB4NzEpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0ZMRUQx X0NUUkwgICAgICAgICAgICAgICAgICAgICAgICAoMHg3MikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2 MF9QTVVfRkxFRF9TVFJCX0NUUkwgICAgICAgICAgICAoMHg3MykKPiA+PiA+ICsjZGVmaW5lIE1U NjM2MF9QTVVfRkxFRDFfU1RSQl9DVFJMMiAgICAgICAgICAoMHg3NCkKPiA+PiA+ICsjZGVmaW5l IE1UNjM2MF9QTVVfRkxFRDFfVE9SX0NUUkwgICAgICAgICAgICAoMHg3NSkKPiA+PiA+ICsjZGVm aW5lIE1UNjM2MF9QTVVfRkxFRDJfQ1RSTCAgICAgICAgICAgICAgICAgICAgICAgICgweDc2KQo+ ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9SRVNWNCAgICAgICAgICAgICAgICAgICAgICgweDc3 KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9GTEVEMl9TVFJCX0NUUkwyICAgICAgICAgICgw eDc4KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9GTEVEMl9UT1JfQ1RSTCAgICAgICAgICAg ICgweDc5KQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9GTEVEX1ZNSURUUktfQ1RSTDEgICAg ICAgICAgICAgICAgKDB4N0EpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0ZMRURfVk1JRF9S VE0gICAgICAgICAgICAgKDB4N0IpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0ZMRURfVk1J RFRSS19DVFJMMiAgICAgICAgICAgICAgICAoMHg3QykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9Q TVVfRkxFRF9QV1NFTCAgICAgICAgICAgICAgICAgICAgICAgICgweDdEKQo+ID4+ID4gKyNkZWZp bmUgTVQ2MzYwX1BNVV9GTEVEX0VOICAgICAgICAgICAgICAgICAgICgweDdFKQo+ID4+ID4gKyNk ZWZpbmUgTVQ2MzYwX1BNVV9GTEVEX0hpZGRlbjEgICAgICAgICAgICAgICAgICAgICAgKDB4N0Yp Cj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQl9FTiAgICAgICAgICAgICAgICAgICAgKDB4 ODApCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjFfSVNOSyAgICAgICAgICAgICAgICAg KDB4ODEpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjJfSVNOSyAgICAgICAgICAgICAg ICAgKDB4ODIpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjNfSVNOSyAgICAgICAgICAg ICAgICAgKDB4ODMpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQl9NTF9JU05LICAgICAg ICAgICAgICAgICAgICAgICAoMHg4NCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfUkdCMV9E SU0gICAgICAgICAgICAgICAgICAoMHg4NSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfUkdC Ml9ESU0gICAgICAgICAgICAgICAgICAoMHg4NikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVf UkdCM19ESU0gICAgICAgICAgICAgICAgICAoMHg4NykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9Q TVVfUkVTVjUgICAgICAgICAgICAgICAgICAgICAoMHg4OCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2 MF9QTVVfUkdCMTJfRnJlcSAgICAgICAgICAgICAgICAgICAgICAgICgweDg5KQo+ID4+ID4gKyNk ZWZpbmUgTVQ2MzYwX1BNVV9SR0IzNF9GcmVxICAgICAgICAgICAgICAgICAgICAgICAgKDB4OEEp Cj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjFfVHIgICAgICAgICAgICAgICAgICAgKDB4 OEIpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjFfVGYgICAgICAgICAgICAgICAgICAg KDB4OEMpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjFfVE9OX1RPRkYgICAgICAgICAg ICAgKDB4OEQpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjJfVHIgICAgICAgICAgICAg ICAgICAgKDB4OEUpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjJfVGYgICAgICAgICAg ICAgICAgICAgKDB4OEYpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjJfVE9OX1RPRkYg ICAgICAgICAgICAgKDB4OTApCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjNfVHIgICAg ICAgICAgICAgICAgICAgKDB4OTEpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjNfVGYg ICAgICAgICAgICAgICAgICAgKDB4OTIpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQjNf VE9OX1RPRkYgICAgICAgICAgICAgKDB4OTMpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JH Ql9IaWRkZW5fQ1RSTDEgICAgICAgICAgKDB4OTQpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1V X1JHQl9IaWRkZW5fQ1RSTDIgICAgICAgICAgKDB4OTUpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBf UE1VX1JFU1Y2ICAgICAgICAgICAgICAgICAgICAgKDB4OTcpCj4gPj4gPiArI2RlZmluZSBNVDYz NjBfUE1VX1NQQVJFMSAgICAgICAgICAgICAgICAgICAgKDB4OUEpCj4gPj4gPiArI2RlZmluZSBN VDYzNjBfUE1VX1NQQVJFMiAgICAgICAgICAgICAgICAgICAgKDB4QTApCj4gPj4gPiArI2RlZmlu ZSBNVDYzNjBfUE1VX1NQQVJFMyAgICAgICAgICAgICAgICAgICAgKDB4QjApCj4gPj4gPiArI2Rl ZmluZSBNVDYzNjBfUE1VX1NQQVJFNCAgICAgICAgICAgICAgICAgICAgKDB4QzApCj4gPj4gPiAr I2RlZmluZSBNVDYzNjBfUE1VX0NIR19JUlExICAgICAgICAgICAgICAgICAgKDB4RDApCj4gPj4g PiArI2RlZmluZSBNVDYzNjBfUE1VX0NIR19JUlEyICAgICAgICAgICAgICAgICAgKDB4RDEpCj4g Pj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NIR19JUlEzICAgICAgICAgICAgICAgICAgKDB4RDIp Cj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NIR19JUlE0ICAgICAgICAgICAgICAgICAgKDB4 RDMpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NIR19JUlE1ICAgICAgICAgICAgICAgICAg KDB4RDQpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NIR19JUlE2ICAgICAgICAgICAgICAg ICAgKDB4RDUpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1FDX0lSUSAgICAgICAgICAgICAg ICAgICAgKDB4RDYpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0ZPRF9JUlEgICAgICAgICAg ICAgICAgICAgKDB4RDcpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0JBU0VfSVJRICAgICAg ICAgICAgICAgICAgKDB4RDgpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0ZMRURfSVJRMSAg ICAgICAgICAgICAgICAgKDB4RDkpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0ZMRURfSVJR MiAgICAgICAgICAgICAgICAgKDB4REEpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1JHQl9J UlEgICAgICAgICAgICAgICAgICAgKDB4REIpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0JV Q0sxX0lSUSAgICAgICAgICAgICAgICAgKDB4REMpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1V X0JVQ0syX0lSUSAgICAgICAgICAgICAgICAgKDB4REQpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBf UE1VX0xET19JUlExICAgICAgICAgICAgICAgICAgKDB4REUpCj4gPj4gPiArI2RlZmluZSBNVDYz NjBfUE1VX0xET19JUlEyICAgICAgICAgICAgICAgICAgKDB4REYpCj4gPj4gPiArI2RlZmluZSBN VDYzNjBfUE1VX0NIR19TVEFUMSAgICAgICAgICAgICAgICAgKDB4RTApCj4gPj4gPiArI2RlZmlu ZSBNVDYzNjBfUE1VX0NIR19TVEFUMiAgICAgICAgICAgICAgICAgKDB4RTEpCj4gPj4gPiArI2Rl ZmluZSBNVDYzNjBfUE1VX0NIR19TVEFUMyAgICAgICAgICAgICAgICAgKDB4RTIpCj4gPj4gPiAr I2RlZmluZSBNVDYzNjBfUE1VX0NIR19TVEFUNCAgICAgICAgICAgICAgICAgKDB4RTMpCj4gPj4g PiArI2RlZmluZSBNVDYzNjBfUE1VX0NIR19TVEFUNSAgICAgICAgICAgICAgICAgKDB4RTQpCj4g Pj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0NIR19TVEFUNiAgICAgICAgICAgICAgICAgKDB4RTUp Cj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX1FDX1NUQVQgICAgICAgICAgICAgICAgICAgKDB4 RTYpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0ZPRF9TVEFUICAgICAgICAgICAgICAgICAg KDB4RTcpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0JBU0VfU1RBVCAgICAgICAgICAgICAg ICAgKDB4RTgpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0ZMRURfU1RBVDEgICAgICAgICAg ICAgICAgICAgICAgICAoMHhFOSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfRkxFRF9TVEFU MiAgICAgICAgICAgICAgICAgICAgICAgICgweEVBKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BN VV9SR0JfU1RBVCAgICAgICAgICAgICAgICAgICgweEVCKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYw X1BNVV9CVUNLMV9TVEFUICAgICAgICAgICAgICAgICAgICAgICAgKDB4RUMpCj4gPj4gPiArI2Rl ZmluZSBNVDYzNjBfUE1VX0JVQ0syX1NUQVQgICAgICAgICAgICAgICAgICAgICAgICAoMHhFRCkK PiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfTERPX1NUQVQxICAgICAgICAgICAgICAgICAoMHhF RSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfTERPX1NUQVQyICAgICAgICAgICAgICAgICAo MHhFRikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX01BU0sxICAgICAgICAgICAgICAg ICAoMHhGMCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX01BU0syICAgICAgICAgICAg ICAgICAoMHhGMSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX01BU0szICAgICAgICAg ICAgICAgICAoMHhGMikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX01BU0s0ICAgICAg ICAgICAgICAgICAoMHhGMykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX01BU0s1ICAg ICAgICAgICAgICAgICAoMHhGNCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQ0hHX01BU0s2 ICAgICAgICAgICAgICAgICAoMHhGNSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfUUNfTUFT SyAgICAgICAgICAgICAgICAgICAoMHhGNikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfRk9E X01BU0sgICAgICAgICAgICAgICAgICAoMHhGNykKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVf QkFTRV9NQVNLICAgICAgICAgICAgICAgICAoMHhGOCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9Q TVVfRkxFRF9NQVNLMSAgICAgICAgICAgICAgICAgICAgICAgICgweEY5KQo+ID4+ID4gKyNkZWZp bmUgTVQ2MzYwX1BNVV9GTEVEX01BU0syICAgICAgICAgICAgICAgICAgICAgICAgKDB4RkEpCj4g Pj4gPiArI2RlZmluZSBNVDYzNjBfUE1VX0ZBVUxUQl9NQVNLICAgICAgICAgICAgICAgICAgICAg ICAoMHhGQikKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTVVfQlVDSzFfTUFTSyAgICAgICAgICAg ICAgICAgICAgICAgICgweEZDKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX1BNVV9CVUNLMl9NQVNL ICAgICAgICAgICAgICAgICAgICAgICAgKDB4RkQpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBfUE1V X0xET19NQVNLMSAgICAgICAgICAgICAgICAgKDB4RkUpCj4gPj4gPiArI2RlZmluZSBNVDYzNjBf UE1VX0xET19NQVNLMiAgICAgICAgICAgICAgICAgKDB4RkYpCj4gPj4gPiArI2RlZmluZSBNVDYz NjBfUE1VX01BWFJFRyAgICAgICAgICAgICAgICAgICAgKE1UNjM2MF9QTVVfTERPX01BU0syKQo+ ID4+ID4gKwo+ID4+ID4gKwo+ID4+ID4gKy8qIE1UNjM2MF9QTVVfSVJRX1NFVCAqLwo+ID4+ID4g KyNkZWZpbmUgTVQ2MzYwX1BNVV9JUlFfUkVHTlVNICAgICAgICAoTVQ2MzYwX1BNVV9MRE9fSVJR MiAtCj4gPj4gPiBNVDYzNjBfUE1VX0NIR19JUlExICsgMSkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2 MF9JUlFfUkVUUklHICAgIEJJVCgyKQo+ID4+ID4gKwo+ID4+ID4gKyNkZWZpbmUgQ0hJUF9WRU5f TUFTSyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgKDB4RjApCj4gPj4gPiArI2RlZmlu ZSBDSElQX1ZFTl9NVDYzNjAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAoMHg1MCkKPiA+ PiA+ICsjZGVmaW5lIENISVBfUkVWX01BU0sgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICgweDBGKQo+ID4+ID4gKwo+ID4+ID4gKy8qIElSUSBkZWZpbml0aW9ucyAqLwo+ID4+Cj4gPj4g UmVtb3ZlIHRoaXMgcGxlYXNlLgo+ID4+Cj4gPj4gPiArc3RydWN0IG10NjM2MF9wbXVfaXJxX2Rl c2Mgewo+ID4+ID4gKyAgICAgY29uc3QgY2hhciAqbmFtZTsKPiA+PiA+ICsgICAgIGlycV9oYW5k bGVyX3QgaXJxX2hhbmRsZXI7Cj4gPj4gPiArfTsKPiA+Pgo+ID4+IFdoZXJlIGlzIHRoaXMgdXNl ZD8KPiA+Pgo+ID4+ID4gKyNkZWZpbmUgIE1UNjM2MF9EVF9WQUxQUk9QKG5hbWUsIHR5cGUpIFwK PiA+PiA+ICsgICAgICAgICAgICAgICAgICAgICB7I25hbWUsIG9mZnNldG9mKHR5cGUsIG5hbWUp fQo+ID4+Cj4gPj4gV2hlcmUgaXMgdGhpcyB1c2VkPwo+ID4+Cj4gPj4gPiArc3RydWN0IG10NjM2 MF92YWxfcHJvcCB7Cj4gPj4gPiArICAgICBjb25zdCBjaGFyICpuYW1lOwo+ID4+ID4gKyAgICAg c2l6ZV90IG9mZnNldDsKPiA+PiA+ICt9Owo+ID4+ID4gKwo+ID4+ID4gK3N0YXRpYyBpbmxpbmUg dm9pZCBtdDYzNjBfZHRfcGFyc2VyX2hlbHBlcihzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wLCB2b2lk Cj4gPj4gPiAqZGF0YSwKPiA+PiA+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgY29uc3Qgc3RydWN0IG10NjM2MF92YWxfcHJvcAo+ID4+ID4gKnByb3BzLAo+ID4+ID4g KyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBpbnQgcHJvcF9jbnQpCj4g Pj4gPiArewo+ID4+ID4gKyAgICAgaW50IGk7Cj4gPj4gPiArCj4gPj4gPiArICAgICBmb3IgKGkg PSAwOyBpIDwgcHJvcF9jbnQ7IGkrKykgewo+ID4+ID4gKyAgICAgICAgICAgICBpZiAodW5saWtl bHkoIXByb3BzW2ldLm5hbWUpKQo+ID4+ID4gKyAgICAgICAgICAgICAgICAgICAgIGNvbnRpbnVl Owo+ID4+ID4gKyAgICAgICAgICAgICBvZl9wcm9wZXJ0eV9yZWFkX3UzMihucCwgcHJvcHNbaV0u bmFtZSwgZGF0YSArCj4gPj4gPiBwcm9wc1tpXS5vZmZzZXQpOwo+ID4+ID4gKyAgICAgfQo+ID4+ ID4gK30KPiA+Pgo+ID4+IFdoYXQgYXJlIHlvdSB1c2luZyB0aGlzIGZvcj8gIFdoeSBpcyB0aGUg c3RhbmRhcmQgQVBJIG5vdCBzdWZmaWNpZW50Pwo+ID4+Cj4gPj4gPiArI2RlZmluZSBNVDYzNjBf UERBVEFfVkFMUFJPUChuYW1lLCB0eXBlLCByZWcsIHNoaWZ0LCBtYXNrLCBmdW5jLCBiYXNlKQo+ ID4+ID4gXAo+ID4+ID4gKyAgICAgICAgICAgICAgICAgICAgIHtvZmZzZXRvZih0eXBlLCBuYW1l KSwgcmVnLCBzaGlmdCwgbWFzaywgZnVuYywKPiA+PiA+IGJhc2V9Cj4gPj4KPiA+PiBXaGVyZSBp cyB0aGlzIHVzZWQ/Cj4gPj4KPiA+PiA+ICtzdHJ1Y3QgbXQ2MzYwX3BkYXRhX3Byb3Agewo+ID4+ ID4gKyAgICAgc2l6ZV90IG9mZnNldDsKPiA+PiA+ICsgICAgIHU4IHJlZzsKPiA+PiA+ICsgICAg IHU4IHNoaWZ0Owo+ID4+ID4gKyAgICAgdTggbWFzazsKPiA+PiA+ICsgICAgIHUzMiAoKnRyYW5z Zm9ybSkodTMyIHZhbCk7Cj4gPj4gPiArICAgICB1OCBiYXNlOwo+ID4+ID4gK307Cj4gPj4gPiAr Cj4gPj4gPiArc3RhdGljIGlubGluZSBpbnQgbXQ2MzYwX3BkYXRhX2FwcGx5X2hlbHBlcih2b2lk ICpjb250ZXh0LCB2b2lkCj4gPj4gPiAqcGRhdGEsCj4gPj4gPiArICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIGNvbnN0IHN0cnVjdCBtdDYzNjBfcGRhdGFfcHJvcAo+ID4+ ID4gKnByb3AsCj4gPj4gPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg IGludCBwcm9wX2NudCkKPiA+PiA+ICt7Cj4gPj4gPiArICAgICBpbnQgaSwgcmV0Owo+ID4+ID4g KyAgICAgdTMyIHZhbDsKPiA+PiA+ICsKPiA+PiA+ICsgICAgIGZvciAoaSA9IDA7IGkgPCBwcm9w X2NudDsgaSsrKSB7Cj4gPj4gPiArICAgICAgICAgICAgIHZhbCA9ICoodTMyICopKHBkYXRhICsg cHJvcFtpXS5vZmZzZXQpOwo+ID4+ID4gKyAgICAgICAgICAgICBpZiAocHJvcFtpXS50cmFuc2Zv cm0pCj4gPj4gPiArICAgICAgICAgICAgICAgICAgICAgdmFsID0gcHJvcFtpXS50cmFuc2Zvcm0o dmFsKTsKPiA+PiA+ICsgICAgICAgICAgICAgdmFsICs9IHByb3BbaV0uYmFzZTsKPiA+PiA+ICsg ICAgICAgICAgICAgcmV0ID0gcmVnbWFwX3VwZGF0ZV9iaXRzKGNvbnRleHQsCj4gPj4gPiArICAg ICAgICAgICAgICAgICAgICAgICAgICBwcm9wW2ldLnJlZywgcHJvcFtpXS5tYXNrLCB2YWwgPDwK PiA+PiA+IHByb3BbaV0uc2hpZnQpOwo+ID4+ID4gKyAgICAgICAgICAgICBpZiAocmV0IDwgMCkK PiA+PiA+ICsgICAgICAgICAgICAgICAgICAgICByZXR1cm4gcmV0Owo+ID4+ID4gKyAgICAgfQo+ ID4+ID4gKyAgICAgcmV0dXJuIDA7Cj4gPj4gPiArfQo+ID4+Cj4gPj4gV2hlcmUgaXMgdGhpcyB1 c2VkPyAgV2hhdCBkb2VzIGl0IGRvPwo+ID4+Cj4gPj4gPiArI2VuZGlmIC8qIF9fTVQ2MzYwX1BS SVZBVEVfSF9fICovCj4gPj4gPiBkaWZmIC0tZ2l0IGEvaW5jbHVkZS9saW51eC9tZmQvbXQ2MzYw LmggYi9pbmNsdWRlL2xpbnV4L21mZC9tdDYzNjAuaAo+ID4+ID4gbmV3IGZpbGUgbW9kZSAxMDA2 NDQKPiA+PiA+IGluZGV4IDAwMDAwMDAuLmJhMmU4MGEKPiA+PiA+IC0tLSAvZGV2L251bGwKPiA+ PiA+ICsrKyBiL2luY2x1ZGUvbGludXgvbWZkL210NjM2MC5oCj4gPj4gPiBAQCAtMCwwICsxLDMz IEBACj4gPj4gPiArLyogU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IEdQTC0yLjAgKi8KPiA+PiA+ ICsvKgo+ID4+ID4gKyAqIENvcHlyaWdodCAoYykgMjAxOSBNZWRpYVRlayBJbmMuCj4gPj4gPiAr ICovCj4gPj4gPiArCj4gPj4gPiArI2lmbmRlZiBfX01UNjM2MF9IX18KPiA+PiA+ICsjZGVmaW5l IF9fTVQ2MzYwX0hfXwo+ID4+ID4gKwo+ID4+ID4gKyNpbmNsdWRlIDxsaW51eC9yZWdtYXAuaD4K PiA+PiA+ICsKPiA+PiA+ICtlbnVtIHsKPiA+PiA+ICsgICAgIE1UNjM2MF9TTEFWRV9QTVUgPSAw LAo+ID4+ID4gKyAgICAgTVQ2MzYwX1NMQVZFX1BNSUMsCj4gPj4gPiArICAgICBNVDYzNjBfU0xB VkVfTERPLAo+ID4+ID4gKyAgICAgTVQ2MzYwX1NMQVZFX1RDUEMsCj4gPj4gPiArICAgICBNVDYz NjBfU0xBVkVfTUFYLAo+ID4+ID4gK307Cj4gPj4gPiArCj4gPj4gPiArI2RlZmluZSBNVDYzNjBf UE1VX1NMQVZFSUQgICAoMHgzNCkKPiA+PiA+ICsjZGVmaW5lIE1UNjM2MF9QTUlDX1NMQVZFSUQg ICgweDFBKQo+ID4+ID4gKyNkZWZpbmUgTVQ2MzYwX0xET19TTEFWRUlEICAgKDB4NjQpCj4gPj4g PiArI2RlZmluZSBNVDYzNjBfVENQQ19TTEFWRUlEICAoMHg0RSkKPiA+Pgo+ID4+IFdoYXQga2lu ZCBvZiBzbGF2ZSBJRD8gIEkyQyBhZGRyZXNzPwo+ID4+Cj4gPj4gPiArc3RydWN0IG10NjM2MF9w bXVfaW5mbyB7Cj4gPj4gPiArICAgICBzdHJ1Y3QgaTJjX2NsaWVudCAqaTJjW01UNjM2MF9TTEFW RV9NQVhdOwo+ID4+ID4gKyAgICAgc3RydWN0IGRldmljZSAqZGV2Owo+ID4+Cj4gPj4gPiArICAg ICBzdHJ1Y3QgcmVnbWFwICpyZWdtYXA7Cj4gPj4gPiArICAgICBzdHJ1Y3QgcmVnbWFwX2lycV9j aGlwX2RhdGEgKmlycV9kYXRhOwo+ID4+ID4gKyAgICAgc3RydWN0IHJlZ21hcF9pcnFfY2hpcCBp cnFfY2hpcDsKPiA+PiA+ICsgICAgIHVuc2lnbmVkIGludCBjaGlwX3JldjsKPiA+Pgo+ID4+IFdo eSBhcmUgeW91IHNhdmluZyB0aGVzZT8KPiA+Pgo+ID4+IFdoZXJlIGRvIHlvdSByZXVzZSB0aGVt Pwo+ID4+Cj4gPj4gPiArfTsKPiA+PiA+ICsKPiA+PiA+ICsjZW5kaWYgLyogX19NVDYzNjBfSF9f ICovCj4gPj4KPiA+CgotLSAKTGVlIEpvbmVzIFvmnY7nkLzmlq9dCkxpbmFybyBTZXJ2aWNlcyBU ZWNobmljYWwgTGVhZApMaW5hcm8ub3JnIOKUgiBPcGVuIHNvdXJjZSBzb2Z0d2FyZSBmb3IgQVJN IFNvQ3MKRm9sbG93IExpbmFybzogRmFjZWJvb2sgfCBUd2l0dGVyIHwgQmxvZwoKX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBt 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X-Received: by 2002:a1c:bc07:: with SMTP id m7mr2697525wmf.103.1571220280517; Wed, 16 Oct 2019 03:04:40 -0700 (PDT) Received: from dell ([95.149.164.86]) by smtp.gmail.com with ESMTPSA id z1sm6671584wrn.57.2019.10.16.03.04.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 16 Oct 2019 03:04:39 -0700 (PDT) Date: Wed, 16 Oct 2019 11:04:38 +0100 From: Lee Jones To: Gene Chen Cc: matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, gene_chen@richtek.com, Wilma.Wu@mediatek.com, shufan_lee@richtek.com, cy_huang@richtek.com Subject: Re: [PATCH v3] mfd: mt6360: add pmic mt6360 driver Message-ID: <20191016100438.GF4365@dell> References: <1569338741-2784-1-git-send-email-gene.chen.richtek@gmail.com> <20191004133324.GE18429@dell> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 15 Oct 2019, Gene Chen wrote: > Hi Lee, > > we find OF_MFD_CELL is not defined in mfd/core.h, which is ready to > merge to next kernel version > https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next-history/+/master/Next/merge.log It's here: Merging mfd/for-mfd-next (38a6fc63a3ea mfd: db8500-prcmu: Example using new OF_MFD_CELL/MFD_CELL_BASIC MACROs) $ git merge mfd/for-mfd-next Merge made by the 'recursive' strategy. drivers/mfd/ab8500-core.c | 138 +++++++++++++------------------------------ drivers/mfd/db8500-prcmu.c | 21 +++---- drivers/mfd/intel-lpss-pci.c | 28 ++++++--- drivers/mfd/ipaq-micro.c | 6 +- drivers/mfd/rk808.c | 22 ++----- include/linux/mfd/core.h | 29 +++++++++ <===== [THIS ONE] include/linux/mfd/rk808.h | 2 +- 7 files changed, 105 insertions(+), 141 deletions(-) https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next-history/+/master/Next/merge.log#4470 > may i ask how can i upstream without this definition? > e.g. we pull this patch and build pass, new patch without add macro define > > 2019-10-08 2:24 GMT+08:00, Gene Chen : > > Hi Jones, > > > > Thanks for review, we will fix some comment which your suggestion in next > > patch > > > > Lee Jones 於 2019年10月4日 週五 下午9:33寫道: > >> > >> Wolfram, > >> > >> Would you be kind enough to grep for your name below? > >> > >> On Tue, 24 Sep 2019, Gene Chen wrote: > >> > >> > From: Gene Chen > >> > > >> > Add mfd driver for mt6360 pmic chip include > >> > Battery Charger/USB_PD/Flash LED/RGB LED/LDO/Buck > >> > > >> > Signed-off-by: Gene Chen >> > --- > >> > drivers/mfd/Kconfig | 12 + > >> > drivers/mfd/Makefile | 1 + > >> > drivers/mfd/mt6360-core.c | 463 > >> > +++++++++++++++++++++++++++++++++++++ > >> > include/linux/mfd/mt6360-private.h | 279 ++++++++++++++++++++++ > >> > include/linux/mfd/mt6360.h | 33 +++ > >> > 5 files changed, 788 insertions(+) > >> > create mode 100644 drivers/mfd/mt6360-core.c > >> > create mode 100644 include/linux/mfd/mt6360-private.h > >> > create mode 100644 include/linux/mfd/mt6360.h > >> > > >> > changelogs between v1 & v2 > >> > - include missing header file > >> > > >> > changelogs between v2 & v3 > >> > - add changelogs > >> > > >> > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > >> > index f129f96..a422c76 100644 > >> > --- a/drivers/mfd/Kconfig > >> > +++ b/drivers/mfd/Kconfig > >> > @@ -862,6 +862,18 @@ config MFD_MAX8998 > >> > additional drivers must be enabled in order to use the > >> > functionality > >> > of the device. > >> > > >> > +config MFD_MT6360 > >> > + tristate "Mediatek MT6360 SubPMIC" > >> > + select MFD_CORE > >> > + select REGMAP_I2C > >> > + select REGMAP_IRQ > >> > + depends on I2C > >> > + help > >> > + Say Y here to enable MT6360 PMU/PMIC/LDO functional support. > >> > + PMU part include charger, flashlight, rgb led > >> > + PMIC part include 2-channel BUCKs and 2-channel LDOs > >> > + LDO part include 4-channel LDOs > >> > >> PMU part includes Charger, Flashlight, RGB and LED > >> PMIC part includes 2-channel BUCKs and 2-channel LDOs > >> LDO part includes 4-channel LDOs > >> > > > > ACK. RGB LED is one of indicator light, only single feature > > > >> > config MFD_MT6397 > >> > tristate "MediaTek MT6397 PMIC Support" > >> > select MFD_CORE > >> > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > >> > index f026ada..77a8f0b 100644 > >> > --- a/drivers/mfd/Makefile > >> > +++ b/drivers/mfd/Makefile > >> > @@ -241,6 +241,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += > >> > intel-soc-pmic.o > >> > obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC) += intel_soc_pmic_bxtwc.o > >> > obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC) += intel_soc_pmic_chtwc.o > >> > obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI) += > >> > intel_soc_pmic_chtdc_ti.o > >> > +obj-$(CONFIG_MFD_MT6360) += mt6360-core.o > >> > obj-$(CONFIG_MFD_MT6397) += mt6397-core.o > >> > > >> > obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o > >> > diff --git a/drivers/mfd/mt6360-core.c b/drivers/mfd/mt6360-core.c > >> > new file mode 100644 > >> > index 0000000..d3580618 > >> > --- /dev/null > >> > +++ b/drivers/mfd/mt6360-core.c > >> > @@ -0,0 +1,463 @@ > >> > +// SPDX-License-Identifier: GPL-2.0 > >> > +/* > >> > + * Copyright (c) 2019 MediaTek Inc. > >> > + */ > >> > + > >> > +#include > >> > +#include > >> > +#include > >> > +#include > >> > +#include > >> > +#include > >> > +#include > >> > +#include > >> > + > >> > +#include > >> > +#include > >> > + > >> > +/* reg 0 -> 0 ~ 7 */ > >> > +#define MT6360_CHG_TREG_EVT (4) > >> > +#define MT6360_CHG_AICR_EVT (5) > >> > +#define MT6360_CHG_MIVR_EVT (6) > >> > +#define MT6360_PWR_RDY_EVT (7) > >> > +/* REG 1 -> 8 ~ 15 */ > >> > +#define MT6360_CHG_BATSYSUV_EVT (9) > >> > +#define MT6360_FLED_CHG_VINOVP_EVT (11) > >> > +#define MT6360_CHG_VSYSUV_EVT (12) > >> > +#define MT6360_CHG_VSYSOV_EVT (13) > >> > +#define MT6360_CHG_VBATOV_EVT (14) > >> > +#define MT6360_CHG_VBUSOV_EVT (15) > >> > +/* REG 2 -> 16 ~ 23 */ > >> > +/* REG 3 -> 24 ~ 31 */ > >> > +#define MT6360_WD_PMU_DET (25) > >> > +#define MT6360_WD_PMU_DONE (26) > >> > +#define MT6360_CHG_TMRI (27) > >> > +#define MT6360_CHG_ADPBADI (29) > >> > +#define MT6360_CHG_RVPI (30) > >> > +#define MT6360_OTPI (31) > >> > +/* REG 4 -> 32 ~ 39 */ > >> > +#define MT6360_CHG_AICCMEASL (32) > >> > +#define MT6360_CHGDET_DONEI (34) > >> > +#define MT6360_WDTMRI (35) > >> > +#define MT6360_SSFINISHI (36) > >> > +#define MT6360_CHG_RECHGI (37) > >> > +#define MT6360_CHG_TERMI (38) > >> > +#define MT6360_CHG_IEOCI (39) > >> > +/* REG 5 -> 40 ~ 47 */ > >> > +#define MT6360_PUMPX_DONEI (40) > >> > +#define MT6360_BAT_OVP_ADC_EVT (41) > >> > +#define MT6360_TYPEC_OTP_EVT (42) > >> > +#define MT6360_ADC_WAKEUP_EVT (43) > >> > +#define MT6360_ADC_DONEI (44) > >> > +#define MT6360_BST_BATUVI (45) > >> > +#define MT6360_BST_VBUSOVI (46) > >> > +#define MT6360_BST_OLPI (47) > >> > +/* REG 6 -> 48 ~ 55 */ > >> > +#define MT6360_ATTACH_I (48) > >> > +#define MT6360_DETACH_I (49) > >> > +#define MT6360_QC30_STPDONE (51) > >> > +#define MT6360_QC_VBUSDET_DONE (52) > >> > +#define MT6360_HVDCP_DET (53) > >> > +#define MT6360_CHGDETI (54) > >> > +#define MT6360_DCDTI (55) > >> > +/* REG 7 -> 56 ~ 63 */ > >> > +#define MT6360_FOD_DONE_EVT (56) > >> > +#define MT6360_FOD_OV_EVT (57) > >> > +#define MT6360_CHRDET_UVP_EVT (58) > >> > +#define MT6360_CHRDET_OVP_EVT (59) > >> > +#define MT6360_CHRDET_EXT_EVT (60) > >> > +#define MT6360_FOD_LR_EVT (61) > >> > +#define MT6360_FOD_HR_EVT (62) > >> > +#define MT6360_FOD_DISCHG_FAIL_EVT (63) > >> > +/* REG 8 -> 64 ~ 71 */ > >> > +#define MT6360_USBID_EVT (64) > >> > +#define MT6360_APWDTRST_EVT (65) > >> > +#define MT6360_EN_EVT (66) > >> > +#define MT6360_QONB_RST_EVT (67) > >> > +#define MT6360_MRSTB_EVT (68) > >> > +#define MT6360_OTP_EVT (69) > >> > +#define MT6360_VDDAOV_EVT (70) > >> > +#define MT6360_SYSUV_EVT (71) > >> > +/* REG 9 -> 72 ~ 79 */ > >> > +#define MT6360_FLED_STRBPIN_EVT (72) > >> > +#define MT6360_FLED_TORPIN_EVT (73) > >> > +#define MT6360_FLED_TX_EVT (74) > >> > +#define MT6360_FLED_LVF_EVT (75) > >> > +#define MT6360_FLED2_SHORT_EVT (78) > >> > +#define MT6360_FLED1_SHORT_EVT (79) > >> > +/* REG 10 -> 80 ~ 87 */ > >> > +#define MT6360_FLED2_STRB_EVT (80) > >> > +#define MT6360_FLED1_STRB_EVT (81) > >> > +#define MT6360_FLED2_STRB_TO_EVT (82) > >> > +#define MT6360_FLED1_STRB_TO_EVT (83) > >> > +#define MT6360_FLED2_TOR_EVT (84) > >> > +#define MT6360_FLED1_TOR_EVT (85) > >> > +/* REG 11 -> 88 ~ 95 */ > >> > +/* REG 12 -> 96 ~ 103 */ > >> > +#define MT6360_BUCK1_PGB_EVT (96) > >> > +#define MT6360_BUCK1_OC_EVT (100) > >> > +#define MT6360_BUCK1_OV_EVT (101) > >> > +#define MT6360_BUCK1_UV_EVT (102) > >> > +/* REG 13 -> 104 ~ 111 */ > >> > +#define MT6360_BUCK2_PGB_EVT (104) > >> > +#define MT6360_BUCK2_OC_EVT (108) > >> > +#define MT6360_BUCK2_OV_EVT (109) > >> > +#define MT6360_BUCK2_UV_EVT (110) > >> > +/* REG 14 -> 112 ~ 119 */ > >> > +#define MT6360_LDO1_OC_EVT (113) > >> > +#define MT6360_LDO2_OC_EVT (114) > >> > +#define MT6360_LDO3_OC_EVT (115) > >> > +#define MT6360_LDO5_OC_EVT (117) > >> > +#define MT6360_LDO6_OC_EVT (118) > >> > +#define MT6360_LDO7_OC_EVT (119) > >> > +/* REG 15 -> 120 ~ 127 */ > >> > +#define MT6360_LDO1_PGB_EVT (121) > >> > +#define MT6360_LDO2_PGB_EVT (122) > >> > +#define MT6360_LDO3_PGB_EVT (123) > >> > +#define MT6360_LDO5_PGB_EVT (125) > >> > +#define MT6360_LDO6_PGB_EVT (126) > >> > +#define MT6360_LDO7_PGB_EVT (127) > >> > + > >> > +#define MT6360_REGMAP_IRQ_REG(_irq_evt) \ > >> > + REGMAP_IRQ_REG(_irq_evt, (_irq_evt) / 8, BIT((_irq_evt) % 8)) > >> > + > >> > +#define MT6360_MFD_CELL(_name) \ > >> > + { \ > >> > + .name = #_name, \ > >> > + .of_compatible = "mediatek," #_name, \ > >> > + .num_resources = ARRAY_SIZE(_name##_resources), \ > >> > + .resources = _name##_resources, \ > >> > + } > >> > >> Please do not roll your own MACROS like this. If they are helpful for > >> you, they are likely to be helpful for others. However, this is your > >> lucky day, as we've been here before. Please rebase onto the MFD tree > >> where you will find some pre-authored macros which aren't too > >> dissimilar to this one. Please use one of those instead. > >> > > > > ACK > > > >> > +static const struct regmap_irq mt6360_pmu_irqs[] = { > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_TREG_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_AICR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_MIVR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_PWR_RDY_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_BATSYSUV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED_CHG_VINOVP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_VSYSUV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_VSYSOV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_VBATOV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_VBUSOV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_WD_PMU_DET), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_WD_PMU_DONE), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_TMRI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_ADPBADI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_RVPI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_OTPI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_AICCMEASL), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHGDET_DONEI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_WDTMRI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_SSFINISHI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_RECHGI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_TERMI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_IEOCI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_PUMPX_DONEI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHG_TREG_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BAT_OVP_ADC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_TYPEC_OTP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_ADC_WAKEUP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_ADC_DONEI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BST_BATUVI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BST_VBUSOVI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BST_OLPI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_ATTACH_I), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_DETACH_I), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_QC30_STPDONE), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_QC_VBUSDET_DONE), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_HVDCP_DET), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHGDETI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_DCDTI), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FOD_DONE_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FOD_OV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHRDET_UVP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHRDET_OVP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_CHRDET_EXT_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FOD_LR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FOD_HR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FOD_DISCHG_FAIL_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_USBID_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_APWDTRST_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_EN_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_QONB_RST_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_MRSTB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_OTP_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_VDDAOV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_SYSUV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED_STRBPIN_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED_TORPIN_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED_TX_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED_LVF_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED2_SHORT_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED1_SHORT_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED2_STRB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED1_STRB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED2_STRB_TO_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED1_STRB_TO_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED2_TOR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_FLED1_TOR_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK1_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK1_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK1_OV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK1_UV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK2_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK2_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK2_OV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_BUCK2_UV_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO1_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO2_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO3_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO5_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO6_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO7_OC_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO1_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO2_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO3_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO5_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO6_PGB_EVT), > >> > + MT6360_REGMAP_IRQ_REG(MT6360_LDO7_PGB_EVT), > >> > +}; > >> > + > >> > +static int mt6360_pmu_handle_post_irq(void *irq_drv_data) > >> > +{ > >> > + struct mt6360_pmu_info *mpi = irq_drv_data; > >> > + > >> > + return regmap_update_bits(mpi->regmap, > >> > + MT6360_PMU_IRQ_SET, MT6360_IRQ_RETRIG, > >> > MT6360_IRQ_RETRIG); > >> > +} > >> > + > >> > +static const struct regmap_irq_chip mt6360_pmu_irq_chip = { > >> > + .irqs = mt6360_pmu_irqs, > >> > + .num_irqs = ARRAY_SIZE(mt6360_pmu_irqs), > >> > + .num_regs = MT6360_PMU_IRQ_REGNUM, > >> > + .mask_base = MT6360_PMU_CHG_MASK1, > >> > + .status_base = MT6360_PMU_CHG_IRQ1, > >> > + .ack_base = MT6360_PMU_CHG_IRQ1, > >> > + .init_ack_masked = true, > >> > + .use_ack = true, > >> > + .handle_post_irq = mt6360_pmu_handle_post_irq, > >> > +}; > >> > + > >> > +static const struct regmap_config mt6360_pmu_regmap_config = { > >> > + .reg_bits = 8, > >> > + .val_bits = 8, > >> > + .max_register = MT6360_PMU_MAXREG, > >> > +}; > >> > + > >> > +static const struct resource mt6360_adc_resources[] = { > >> > + DEFINE_RES_IRQ_NAMED(MT6360_ADC_DONEI, "adc_donei"), > >> > +}; > >> > + > >> > +static const struct resource mt6360_chg_resources[] = { > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_TREG_EVT, "chg_treg_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_PWR_RDY_EVT, "pwr_rdy_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_BATSYSUV_EVT, > >> > "chg_batsysuv_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSUV_EVT, "chg_vsysuv_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VSYSOV_EVT, "chg_vsysov_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBATOV_EVT, "chg_vbatov_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_VBUSOV_EVT, "chg_vbusov_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_AICCMEASL, "chg_aiccmeasl"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_WDTMRI, "wdtmri"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_RECHGI, "chg_rechgi"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_TERMI, "chg_termi"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHG_IEOCI, "chg_ieoci"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_PUMPX_DONEI, "pumpx_donei"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_ATTACH_I, "attach_i"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_CHRDET_EXT_EVT, "chrdet_ext_evt"), > >> > +}; > >> > + > >> > +static const struct resource mt6360_led_resources[] = { > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED_CHG_VINOVP_EVT, > >> > "fled_chg_vinovp_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED_LVF_EVT, "fled_lvf_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED2_SHORT_EVT, "fled2_short_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED1_SHORT_EVT, "fled1_short_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED2_STRB_TO_EVT, > >> > "fled2_strb_to_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_FLED1_STRB_TO_EVT, > >> > "fled1_strb_to_evt"), > >> > +}; > >> > + > >> > +static const struct resource mt6360_pmic_resources[] = { > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_PGB_EVT, "buck1_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OC_EVT, "buck1_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_OV_EVT, "buck1_ov_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK1_UV_EVT, "buck1_uv_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_PGB_EVT, "buck2_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OC_EVT, "buck2_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_OV_EVT, "buck2_ov_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_BUCK2_UV_EVT, "buck2_uv_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO6_OC_EVT, "ldo6_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO7_OC_EVT, "ldo7_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO6_PGB_EVT, "ldo6_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO7_PGB_EVT, "ldo7_pgb_evt"), > >> > +}; > >> > + > >> > +static const struct resource mt6360_ldo_resources[] = { > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO1_OC_EVT, "ldo1_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO2_OC_EVT, "ldo2_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO3_OC_EVT, "ldo3_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO5_OC_EVT, "ldo5_oc_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO1_PGB_EVT, "ldo1_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO2_PGB_EVT, "ldo2_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO3_PGB_EVT, "ldo3_pgb_evt"), > >> > + DEFINE_RES_IRQ_NAMED(MT6360_LDO5_PGB_EVT, "ldo5_pgb_evt"), > >> > +}; > >> > + > >> > +static const struct mfd_cell mt6360_devs[] = { > >> > + MT6360_MFD_CELL(mt6360_adc), > >> > + MT6360_MFD_CELL(mt6360_chg), > >> > + MT6360_MFD_CELL(mt6360_led), > >> > + MT6360_MFD_CELL(mt6360_pmic), > >> > + MT6360_MFD_CELL(mt6360_ldo), > >> > + /* tcpc dev */ > >> > + { > >> > + .name = "mt6360_tcpc", > >> > + .of_compatible = "mediatek,mt6360_tcpc", > >> > >> There is a macro for this too (OF_MFD_CELL()) > >> > > > > ACK > > > >> > + }, > >> > +}; > >> > + > >> > +static const unsigned short mt6360_slave_addr[MT6360_SLAVE_MAX] = { > >> > + MT6360_PMU_SLAVEID, > >> > + MT6360_PMIC_SLAVEID, > >> > + MT6360_LDO_SLAVEID, > >> > + MT6360_TCPC_SLAVEID, > >> > +}; > >> > + > >> > +static int mt6360_pmu_probe(struct i2c_client *client, > >> > + const struct i2c_device_id *id) > >> > >> If you use .probe_new (see below) you can omit the 'id' param. > >> > > > > ACK > > > >> > +{ > >> > + struct mt6360_pmu_info *mpi; > >> > >> We normally call this ddata. > >> > > > > ACK > > > >> > + unsigned int reg_data = 0; > >> > + int i, ret; > >> > + > >> > + mpi = devm_kzalloc(&client->dev, sizeof(*mpi), GFP_KERNEL); > >> > + if (!mpi) > >> > + return -ENOMEM; > >> > >> '\n' here. > >> > > > > ACK > > > >> > + mpi->dev = &client->dev; > >> > + i2c_set_clientdata(client, mpi); > >> > + > >> > + /* regmap regiser */ > >> > >> This comment is spelt incorrectly and doesn't really add anything. > >> > > > > ACK > > > >> > + mpi->regmap = devm_regmap_init_i2c(client, > >> > &mt6360_pmu_regmap_config); > >> > + if (IS_ERR(mpi->regmap)) { > >> > + dev_err(&client->dev, "regmap register fail\n"); > >> > >> "Failed to register regmap" > >> > > > > ACK > > > >> > + return PTR_ERR(mpi->regmap); > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + /* chip id check */ > >> > >> Again, the code is pretty obvious. > >> > > > > ACK > > > >> > + ret = regmap_read(mpi->regmap, MT6360_PMU_DEV_INFO, ®_data); > >> > + if (ret < 0) { > >> > + dev_err(&client->dev, "device not found\n"); > >> > >> "Device not found" > >> > > > > ACK > > > >> > + return ret; > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + if ((reg_data & CHIP_VEN_MASK) != CHIP_VEN_MT6360) { > >> > + dev_err(&client->dev, "not mt6360 chip\n"); > >> > >> "Device not supported" > >> > > > > ACK > > > >> > + return -ENODEV; > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + mpi->chip_rev = reg_data & CHIP_REV_MASK; > >> > >> Do this above the check, then do > >> > >> (mpi->chip_rev != CHIP_VEN_MT6360) > >> > >> ... above. > >> > > > > ACK > > > >> > + /* irq register */ > >> > >> Please remove all of these comments. > >> > > > > ACK > > > >> > + memcpy(&mpi->irq_chip, &mt6360_pmu_irq_chip, > >> > sizeof(mpi->irq_chip)); > >> > >> Why do we need to make a copy of it? > >> > > > > consider of using mutiple mt6360 chips, we can seperate diff i2c > > irq_chip.name by device_name originally > > but we can't find silimar case by overview other mfd driver > > we will delete this > > > >> > + mpi->irq_chip.name = dev_name(&client->dev); > >> > >> We already know the name. Why do we need to do this dynamically? > >> > > > > same as above > > > >> > + mpi->irq_chip.irq_drv_data = mpi; > >> > >> We already saved ddata. Why do we need to save it here as well? > >> > > > > we implement ops ".handle_post_irq" for irq retrigger when irq stuck keep > > low > > > >> > + ret = devm_regmap_add_irq_chip(&client->dev, mpi->regmap, > >> > client->irq, > >> > + IRQF_TRIGGER_FALLING, 0, > >> > &mpi->irq_chip, > >> > + &mpi->irq_data); > >> > + if (ret < 0) { > >> > >> Is (ret > 0) valid? > >> > > > > we consider mt6360 driver need add irq_chip for full functionality > > > >> > + dev_err(&client->dev, "regmap irq chip add fail\n"); > >> > >> "Failed to add Regmap IRQ Chip" > >> > > > > ACK > > > >> > + return ret; > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + /* new i2c slave device */ > >> > + for (i = 0; i < MT6360_SLAVE_MAX; i++) { > >> > + if (mt6360_slave_addr[i] == client->addr) { > >> > + mpi->i2c[i] = client; > >> > + continue; > >> > + } > >> > + mpi->i2c[i] = i2c_new_dummy(client->adapter, > >> > + mt6360_slave_addr[i]); > >> > + if (!mpi->i2c[i]) { > >> > + dev_err(&client->dev, "new i2c dev [%d] fail\n", > >> > i); > >> > + ret = -ENODEV; > >> > + goto out; > >> > + } > >> > + i2c_set_clientdata(mpi->i2c[i], mpi); > >> > + } > >> > >> This doesn't look right to me. > >> > >> Wolfram, would you be kind enough to take a look? > >> > >> '\n' here. > >> > > > > ACK > > > >> > + /* mfd cell register */ > >> > + ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_AUTO, > >> > + mt6360_devs, ARRAY_SIZE(mt6360_devs), > >> > NULL, > >> > + 0, > >> > regmap_irq_get_domain(mpi->irq_data)); > >> > + if (ret < 0) { > >> > + dev_err(&client->dev, "mfd add cells fail\n"); > >> > + goto out; > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + dev_info(&client->dev, "Successfully probed\n"); > >> > >> Please remove this line. It doesn't provide anything. > >> > > > > ACK > > > >> > + return 0; > >> > +out: > >> > + while (--i >= 0) { > >> > + if (mpi->i2c[i]->addr == client->addr) > >> > + continue; > >> > + i2c_unregister_device(mpi->i2c[i]); > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + return ret; > >> > +} > >> > + > >> > +static int mt6360_pmu_remove(struct i2c_client *client) > >> > +{ > >> > + struct mt6360_pmu_info *mpi = i2c_get_clientdata(client); > >> > + int i; > >> > + > >> > + for (i = 0; i < MT6360_SLAVE_MAX; i++) { > >> > + if (mpi->i2c[i]->addr == client->addr) > >> > + continue; > >> > + i2c_unregister_device(mpi->i2c[i]); > >> > + } > >> > >> '\n' here. > >> > > > > ACK > > > >> > + return 0; > >> > +} > >> > + > >> > +static int __maybe_unused mt6360_pmu_suspend(struct device *dev) > >> > +{ > >> > + struct i2c_client *i2c = to_i2c_client(dev); > >> > + > >> > + if (device_may_wakeup(dev)) > >> > + enable_irq_wake(i2c->irq); > >> > >> '\n' here. > >> > > > > ACK > > > >> > + return 0; > >> > +} > >> > + > >> > +static int __maybe_unused mt6360_pmu_resume(struct device *dev) > >> > +{ > >> > + > >> > + struct i2c_client *i2c = to_i2c_client(dev); > >> > + > >> > + if (device_may_wakeup(dev)) > >> > + disable_irq_wake(i2c->irq); > >> > >> '\n' here. > >> > > > > ACK > > > >> > + return 0; > >> > +} > >> > + > >> > +static SIMPLE_DEV_PM_OPS(mt6360_pmu_pm_ops, > >> > + mt6360_pmu_suspend, mt6360_pmu_resume); > >> > + > >> > +static const struct of_device_id __maybe_unused mt6360_pmu_of_id[] = { > >> > + { .compatible = "mediatek,mt6360_pmu", }, > >> > + {}, > >> > +}; > >> > +MODULE_DEVICE_TABLE(of, mt6360_pmu_of_id); > >> > + > >> > +static const struct i2c_device_id mt6360_pmu_id[] = { > >> > + { "mt6360_pmu", 0 }, > >> > + {}, > >> > +}; > >> > +MODULE_DEVICE_TABLE(i2c, mt6360_pmu_id); > >> > >> If you use .probe_new (see below, you can remove this table. > >> > > > > ACK > > > >> > +static struct i2c_driver mt6360_pmu_driver = { > >> > + .driver = { > >> > + .name = "mt6360_pmu", > >> > + .owner = THIS_MODULE, > >> > >> This is no longer required. > >> > > > > ACK > > > >> > + .pm = &mt6360_pmu_pm_ops, > >> > + .of_match_table = of_match_ptr(mt6360_pmu_of_id), > >> > + }, > >> > + .probe = mt6360_pmu_probe, > >> > >> Use .probe_new here. > >> > > > > ACK > > > >> > + .remove = mt6360_pmu_remove, > >> > + .id_table = mt6360_pmu_id, > >> > +}; > >> > +module_i2c_driver(mt6360_pmu_driver); > >> > + > >> > +MODULE_AUTHOR("CY_Huang "); > >> > +MODULE_DESCRIPTION("MT6360 PMU I2C Driver"); > >> > +MODULE_LICENSE("GPL"); > >> > +MODULE_VERSION("1.0.0"); > >> > diff --git a/include/linux/mfd/mt6360-private.h > >> > b/include/linux/mfd/mt6360-private.h > >> > new file mode 100644 > >> > index 0000000..b07b3d9 > >> > --- /dev/null > >> > +++ b/include/linux/mfd/mt6360-private.h > >> > >> Why do you need 2 header files? > >> > > > > According to our architecture as attachment, > > mt6360 have 4 i2c slave address for different parts > > so we set whole register table in mt6360-private.h, it will be > > included by other modules > > we will delete it next patch > > and we will add until we use it > > > >> > @@ -0,0 +1,279 @@ > >> > +/* SPDX-License-Identifier: GPL-2.0 */ > >> > +/* > >> > + * Copyright (c) 2019 MediaTek Inc. > >> > + */ > >> > + > >> > +#ifndef __MT6360_PRIVATE_H__ > >> > +#define __MT6360_PRIVATE_H__ > >> > >> __MFD_MT6360_H__ > >> > >> > +#include > >> > + > >> > +/* PMU register defininition */ > >> > +#define MT6360_PMU_DEV_INFO (0x00) > >> > +#define MT6360_PMU_CORE_CTRL1 (0x01) > >> > +#define MT6360_PMU_RST1 (0x02) > >> > +#define MT6360_PMU_CRCEN (0x03) > >> > +#define MT6360_PMU_RST_PAS_CODE1 (0x04) > >> > +#define MT6360_PMU_RST_PAS_CODE2 (0x05) > >> > +#define MT6360_PMU_CORE_CTRL2 (0x06) > >> > +#define MT6360_PMU_TM_PAS_CODE1 (0x07) > >> > +#define MT6360_PMU_TM_PAS_CODE2 (0x08) > >> > +#define MT6360_PMU_TM_PAS_CODE3 (0x09) > >> > +#define MT6360_PMU_TM_PAS_CODE4 (0x0A) > >> > +#define MT6360_PMU_IRQ_IND (0x0B) > >> > +#define MT6360_PMU_IRQ_MASK (0x0C) > >> > +#define MT6360_PMU_IRQ_SET (0x0D) > >> > +#define MT6360_PMU_SHDN_CTRL (0x0E) > >> > +#define MT6360_PMU_TM_INF (0x0F) > >> > +#define MT6360_PMU_I2C_CTRL (0x10) > >> > +#define MT6360_PMU_CHG_CTRL1 (0x11) > >> > +#define MT6360_PMU_CHG_CTRL2 (0x12) > >> > +#define MT6360_PMU_CHG_CTRL3 (0x13) > >> > +#define MT6360_PMU_CHG_CTRL4 (0x14) > >> > +#define MT6360_PMU_CHG_CTRL5 (0x15) > >> > +#define MT6360_PMU_CHG_CTRL6 (0x16) > >> > +#define MT6360_PMU_CHG_CTRL7 (0x17) > >> > +#define MT6360_PMU_CHG_CTRL8 (0x18) > >> > +#define MT6360_PMU_CHG_CTRL9 (0x19) > >> > +#define MT6360_PMU_CHG_CTRL10 (0x1A) > >> > +#define MT6360_PMU_CHG_CTRL11 (0x1B) > >> > +#define MT6360_PMU_CHG_CTRL12 (0x1C) > >> > +#define MT6360_PMU_CHG_CTRL13 (0x1D) > >> > +#define MT6360_PMU_CHG_CTRL14 (0x1E) > >> > +#define MT6360_PMU_CHG_CTRL15 (0x1F) > >> > +#define MT6360_PMU_CHG_CTRL16 (0x20) > >> > +#define MT6360_PMU_CHG_AICC_RESULT (0x21) > >> > +#define MT6360_PMU_DEVICE_TYPE (0x22) > >> > +#define MT6360_PMU_QC_CONTROL1 (0x23) > >> > +#define MT6360_PMU_QC_CONTROL2 (0x24) > >> > +#define MT6360_PMU_QC30_CONTROL1 (0x25) > >> > +#define MT6360_PMU_QC30_CONTROL2 (0x26) > >> > +#define MT6360_PMU_USB_STATUS1 (0x27) > >> > +#define MT6360_PMU_QC_STATUS1 (0x28) > >> > +#define MT6360_PMU_QC_STATUS2 (0x29) > >> > +#define MT6360_PMU_CHG_PUMP (0x2A) > >> > +#define MT6360_PMU_CHG_CTRL17 (0x2B) > >> > +#define MT6360_PMU_CHG_CTRL18 (0x2C) > >> > +#define MT6360_PMU_CHRDET_CTRL1 (0x2D) > >> > +#define MT6360_PMU_CHRDET_CTRL2 (0x2E) > >> > +#define MT6360_PMU_DPDN_CTRL (0x2F) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL1 (0x30) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL2 (0x31) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL3 (0x32) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL4 (0x33) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL5 (0x34) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL6 (0x35) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL7 (0x36) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL8 (0x37) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL9 (0x38) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL10 (0x39) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL11 (0x3A) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL12 (0x3B) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL13 (0x3C) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL14 (0x3D) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL15 (0x3E) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL16 (0x3F) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL17 (0x40) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL18 (0x41) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL19 (0x42) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL20 (0x43) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL21 (0x44) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL22 (0x45) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL23 (0x46) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL24 (0x47) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL25 (0x48) > >> > +#define MT6360_PMU_BC12_CTRL (0x49) > >> > +#define MT6360_PMU_CHG_STAT (0x4A) > >> > +#define MT6360_PMU_RESV1 (0x4B) > >> > +#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEH (0x4E) > >> > +#define MT6360_PMU_TYPEC_OTP_TH_SEL_CODEL (0x4F) > >> > +#define MT6360_PMU_TYPEC_OTP_HYST_TH (0x50) > >> > +#define MT6360_PMU_TYPEC_OTP_CTRL (0x51) > >> > +#define MT6360_PMU_ADC_BAT_DATA_H (0x52) > >> > +#define MT6360_PMU_ADC_BAT_DATA_L (0x53) > >> > +#define MT6360_PMU_IMID_BACKBST_ON (0x54) > >> > +#define MT6360_PMU_IMID_BACKBST_OFF (0x55) > >> > +#define MT6360_PMU_ADC_CONFIG (0x56) > >> > +#define MT6360_PMU_ADC_EN2 (0x57) > >> > +#define MT6360_PMU_ADC_IDLE_T (0x58) > >> > +#define MT6360_PMU_ADC_RPT_1 (0x5A) > >> > +#define MT6360_PMU_ADC_RPT_2 (0x5B) > >> > +#define MT6360_PMU_ADC_RPT_3 (0x5C) > >> > +#define MT6360_PMU_ADC_RPT_ORG1 (0x5D) > >> > +#define MT6360_PMU_ADC_RPT_ORG2 (0x5E) > >> > +#define MT6360_PMU_BAT_OVP_TH_SEL_CODEH (0x5F) > >> > +#define MT6360_PMU_BAT_OVP_TH_SEL_CODEL (0x60) > >> > +#define MT6360_PMU_CHG_CTRL19 (0x61) > >> > +#define MT6360_PMU_VDDASUPPLY (0x62) > >> > +#define MT6360_PMU_BC12_MANUAL (0x63) > >> > +#define MT6360_PMU_CHGDET_FUNC (0x64) > >> > +#define MT6360_PMU_FOD_CTRL (0x65) > >> > +#define MT6360_PMU_CHG_CTRL20 (0x66) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL26 (0x67) > >> > +#define MT6360_PMU_CHG_HIDDEN_CTRL27 (0x68) > >> > +#define MT6360_PMU_RESV2 (0x69) > >> > +#define MT6360_PMU_USBID_CTRL1 (0x6D) > >> > +#define MT6360_PMU_USBID_CTRL2 (0x6E) > >> > +#define MT6360_PMU_USBID_CTRL3 (0x6F) > >> > +#define MT6360_PMU_FLED_CFG (0x70) > >> > +#define MT6360_PMU_RESV3 (0x71) > >> > +#define MT6360_PMU_FLED1_CTRL (0x72) > >> > +#define MT6360_PMU_FLED_STRB_CTRL (0x73) > >> > +#define MT6360_PMU_FLED1_STRB_CTRL2 (0x74) > >> > +#define MT6360_PMU_FLED1_TOR_CTRL (0x75) > >> > +#define MT6360_PMU_FLED2_CTRL (0x76) > >> > +#define MT6360_PMU_RESV4 (0x77) > >> > +#define MT6360_PMU_FLED2_STRB_CTRL2 (0x78) > >> > +#define MT6360_PMU_FLED2_TOR_CTRL (0x79) > >> > +#define MT6360_PMU_FLED_VMIDTRK_CTRL1 (0x7A) > >> > +#define MT6360_PMU_FLED_VMID_RTM (0x7B) > >> > +#define MT6360_PMU_FLED_VMIDTRK_CTRL2 (0x7C) > >> > +#define MT6360_PMU_FLED_PWSEL (0x7D) > >> > +#define MT6360_PMU_FLED_EN (0x7E) > >> > +#define MT6360_PMU_FLED_Hidden1 (0x7F) > >> > +#define MT6360_PMU_RGB_EN (0x80) > >> > +#define MT6360_PMU_RGB1_ISNK (0x81) > >> > +#define MT6360_PMU_RGB2_ISNK (0x82) > >> > +#define MT6360_PMU_RGB3_ISNK (0x83) > >> > +#define MT6360_PMU_RGB_ML_ISNK (0x84) > >> > +#define MT6360_PMU_RGB1_DIM (0x85) > >> > +#define MT6360_PMU_RGB2_DIM (0x86) > >> > +#define MT6360_PMU_RGB3_DIM (0x87) > >> > +#define MT6360_PMU_RESV5 (0x88) > >> > +#define MT6360_PMU_RGB12_Freq (0x89) > >> > +#define MT6360_PMU_RGB34_Freq (0x8A) > >> > +#define MT6360_PMU_RGB1_Tr (0x8B) > >> > +#define MT6360_PMU_RGB1_Tf (0x8C) > >> > +#define MT6360_PMU_RGB1_TON_TOFF (0x8D) > >> > +#define MT6360_PMU_RGB2_Tr (0x8E) > >> > +#define MT6360_PMU_RGB2_Tf (0x8F) > >> > +#define MT6360_PMU_RGB2_TON_TOFF (0x90) > >> > +#define MT6360_PMU_RGB3_Tr (0x91) > >> > +#define MT6360_PMU_RGB3_Tf (0x92) > >> > +#define MT6360_PMU_RGB3_TON_TOFF (0x93) > >> > +#define MT6360_PMU_RGB_Hidden_CTRL1 (0x94) > >> > +#define MT6360_PMU_RGB_Hidden_CTRL2 (0x95) > >> > +#define MT6360_PMU_RESV6 (0x97) > >> > +#define MT6360_PMU_SPARE1 (0x9A) > >> > +#define MT6360_PMU_SPARE2 (0xA0) > >> > +#define MT6360_PMU_SPARE3 (0xB0) > >> > +#define MT6360_PMU_SPARE4 (0xC0) > >> > +#define MT6360_PMU_CHG_IRQ1 (0xD0) > >> > +#define MT6360_PMU_CHG_IRQ2 (0xD1) > >> > +#define MT6360_PMU_CHG_IRQ3 (0xD2) > >> > +#define MT6360_PMU_CHG_IRQ4 (0xD3) > >> > +#define MT6360_PMU_CHG_IRQ5 (0xD4) > >> > +#define MT6360_PMU_CHG_IRQ6 (0xD5) > >> > +#define MT6360_PMU_QC_IRQ (0xD6) > >> > +#define MT6360_PMU_FOD_IRQ (0xD7) > >> > +#define MT6360_PMU_BASE_IRQ (0xD8) > >> > +#define MT6360_PMU_FLED_IRQ1 (0xD9) > >> > +#define MT6360_PMU_FLED_IRQ2 (0xDA) > >> > +#define MT6360_PMU_RGB_IRQ (0xDB) > >> > +#define MT6360_PMU_BUCK1_IRQ (0xDC) > >> > +#define MT6360_PMU_BUCK2_IRQ (0xDD) > >> > +#define MT6360_PMU_LDO_IRQ1 (0xDE) > >> > +#define MT6360_PMU_LDO_IRQ2 (0xDF) > >> > +#define MT6360_PMU_CHG_STAT1 (0xE0) > >> > +#define MT6360_PMU_CHG_STAT2 (0xE1) > >> > +#define MT6360_PMU_CHG_STAT3 (0xE2) > >> > +#define MT6360_PMU_CHG_STAT4 (0xE3) > >> > +#define MT6360_PMU_CHG_STAT5 (0xE4) > >> > +#define MT6360_PMU_CHG_STAT6 (0xE5) > >> > +#define MT6360_PMU_QC_STAT (0xE6) > >> > +#define MT6360_PMU_FOD_STAT (0xE7) > >> > +#define MT6360_PMU_BASE_STAT (0xE8) > >> > +#define MT6360_PMU_FLED_STAT1 (0xE9) > >> > +#define MT6360_PMU_FLED_STAT2 (0xEA) > >> > +#define MT6360_PMU_RGB_STAT (0xEB) > >> > +#define MT6360_PMU_BUCK1_STAT (0xEC) > >> > +#define MT6360_PMU_BUCK2_STAT (0xED) > >> > +#define MT6360_PMU_LDO_STAT1 (0xEE) > >> > +#define MT6360_PMU_LDO_STAT2 (0xEF) > >> > +#define MT6360_PMU_CHG_MASK1 (0xF0) > >> > +#define MT6360_PMU_CHG_MASK2 (0xF1) > >> > +#define MT6360_PMU_CHG_MASK3 (0xF2) > >> > +#define MT6360_PMU_CHG_MASK4 (0xF3) > >> > +#define MT6360_PMU_CHG_MASK5 (0xF4) > >> > +#define MT6360_PMU_CHG_MASK6 (0xF5) > >> > +#define MT6360_PMU_QC_MASK (0xF6) > >> > +#define MT6360_PMU_FOD_MASK (0xF7) > >> > +#define MT6360_PMU_BASE_MASK (0xF8) > >> > +#define MT6360_PMU_FLED_MASK1 (0xF9) > >> > +#define MT6360_PMU_FLED_MASK2 (0xFA) > >> > +#define MT6360_PMU_FAULTB_MASK (0xFB) > >> > +#define MT6360_PMU_BUCK1_MASK (0xFC) > >> > +#define MT6360_PMU_BUCK2_MASK (0xFD) > >> > +#define MT6360_PMU_LDO_MASK1 (0xFE) > >> > +#define MT6360_PMU_LDO_MASK2 (0xFF) > >> > +#define MT6360_PMU_MAXREG (MT6360_PMU_LDO_MASK2) > >> > + > >> > + > >> > +/* MT6360_PMU_IRQ_SET */ > >> > +#define MT6360_PMU_IRQ_REGNUM (MT6360_PMU_LDO_IRQ2 - > >> > MT6360_PMU_CHG_IRQ1 + 1) > >> > +#define MT6360_IRQ_RETRIG BIT(2) > >> > + > >> > +#define CHIP_VEN_MASK (0xF0) > >> > +#define CHIP_VEN_MT6360 (0x50) > >> > +#define CHIP_REV_MASK (0x0F) > >> > + > >> > +/* IRQ definitions */ > >> > >> Remove this please. > >> > >> > +struct mt6360_pmu_irq_desc { > >> > + const char *name; > >> > + irq_handler_t irq_handler; > >> > +}; > >> > >> Where is this used? > >> > >> > +#define MT6360_DT_VALPROP(name, type) \ > >> > + {#name, offsetof(type, name)} > >> > >> Where is this used? > >> > >> > +struct mt6360_val_prop { > >> > + const char *name; > >> > + size_t offset; > >> > +}; > >> > + > >> > +static inline void mt6360_dt_parser_helper(struct device_node *np, void > >> > *data, > >> > + const struct mt6360_val_prop > >> > *props, > >> > + int prop_cnt) > >> > +{ > >> > + int i; > >> > + > >> > + for (i = 0; i < prop_cnt; i++) { > >> > + if (unlikely(!props[i].name)) > >> > + continue; > >> > + of_property_read_u32(np, props[i].name, data + > >> > props[i].offset); > >> > + } > >> > +} > >> > >> What are you using this for? Why is the standard API not sufficient? > >> > >> > +#define MT6360_PDATA_VALPROP(name, type, reg, shift, mask, func, base) > >> > \ > >> > + {offsetof(type, name), reg, shift, mask, func, > >> > base} > >> > >> Where is this used? > >> > >> > +struct mt6360_pdata_prop { > >> > + size_t offset; > >> > + u8 reg; > >> > + u8 shift; > >> > + u8 mask; > >> > + u32 (*transform)(u32 val); > >> > + u8 base; > >> > +}; > >> > + > >> > +static inline int mt6360_pdata_apply_helper(void *context, void > >> > *pdata, > >> > + const struct mt6360_pdata_prop > >> > *prop, > >> > + int prop_cnt) > >> > +{ > >> > + int i, ret; > >> > + u32 val; > >> > + > >> > + for (i = 0; i < prop_cnt; i++) { > >> > + val = *(u32 *)(pdata + prop[i].offset); > >> > + if (prop[i].transform) > >> > + val = prop[i].transform(val); > >> > + val += prop[i].base; > >> > + ret = regmap_update_bits(context, > >> > + prop[i].reg, prop[i].mask, val << > >> > prop[i].shift); > >> > + if (ret < 0) > >> > + return ret; > >> > + } > >> > + return 0; > >> > +} > >> > >> Where is this used? What does it do? > >> > >> > +#endif /* __MT6360_PRIVATE_H__ */ > >> > diff --git a/include/linux/mfd/mt6360.h b/include/linux/mfd/mt6360.h > >> > new file mode 100644 > >> > index 0000000..ba2e80a > >> > --- /dev/null > >> > +++ b/include/linux/mfd/mt6360.h > >> > @@ -0,0 +1,33 @@ > >> > +/* SPDX-License-Identifier: GPL-2.0 */ > >> > +/* > >> > + * Copyright (c) 2019 MediaTek Inc. > >> > + */ > >> > + > >> > +#ifndef __MT6360_H__ > >> > +#define __MT6360_H__ > >> > + > >> > +#include > >> > + > >> > +enum { > >> > + MT6360_SLAVE_PMU = 0, > >> > + MT6360_SLAVE_PMIC, > >> > + MT6360_SLAVE_LDO, > >> > + MT6360_SLAVE_TCPC, > >> > + MT6360_SLAVE_MAX, > >> > +}; > >> > + > >> > +#define MT6360_PMU_SLAVEID (0x34) > >> > +#define MT6360_PMIC_SLAVEID (0x1A) > >> > +#define MT6360_LDO_SLAVEID (0x64) > >> > +#define MT6360_TCPC_SLAVEID (0x4E) > >> > >> What kind of slave ID? I2C address? > >> > >> > +struct mt6360_pmu_info { > >> > + struct i2c_client *i2c[MT6360_SLAVE_MAX]; > >> > + struct device *dev; > >> > >> > + struct regmap *regmap; > >> > + struct regmap_irq_chip_data *irq_data; > >> > + struct regmap_irq_chip irq_chip; > >> > + unsigned int chip_rev; > >> > >> Why are you saving these? > >> > >> Where do you reuse them? > >> > >> > +}; > >> > + > >> > +#endif /* __MT6360_H__ */ > >> > > -- Lee Jones [李琼斯] Linaro Services Technical Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog