From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 99D73CA9EA1 for ; Fri, 18 Oct 2019 13:49:01 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71E8E222BD for ; Fri, 18 Oct 2019 13:49:01 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 71E8E222BD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=redhat.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iLSbw-0004eM-NK; Fri, 18 Oct 2019 13:48:08 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57] helo=us1-amaz-eas2.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1iLSbv-0004eG-Sa for xen-devel@lists.xenproject.org; Fri, 18 Oct 2019 13:48:07 +0000 X-Inumbo-ID: e9fb3636-f1ad-11e9-93f5-12813bfff9fa Received: from mx1.redhat.com (unknown [209.132.183.28]) by us1-amaz-eas2.inumbo.com (Halon) with ESMTPS id e9fb3636-f1ad-11e9-93f5-12813bfff9fa; Fri, 18 Oct 2019 13:48:07 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 8EBD93078468; Fri, 18 Oct 2019 13:48:06 +0000 (UTC) Received: from x1w.redhat.com (unknown [10.40.205.74]) by smtp.corp.redhat.com (Postfix) with ESMTPS id F2DF260BF4; Fri, 18 Oct 2019 13:47:56 +0000 (UTC) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Fri, 18 Oct 2019 15:47:34 +0200 Message-Id: <20191018134754.16362-1-philmd@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.41]); Fri, 18 Oct 2019 13:48:06 +0000 (UTC) Subject: [Xen-devel] [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , Marcel Apfelbaum , "Michael S. Tsirkin" , Paul Durrant , Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Markovic , Igor Mammedov , Anthony Perard , xen-devel@lists.xenproject.org, Aleksandar Rikalo , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Eduardo Habkost Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" Q2hhbmdlcyBzaW5jZSB2MSBbMF06Ci0gUmVtb3ZlZCBwYXRjaCByZWludHJvZHVjaW5nIERPX1VQ Q0FTVCgpIHVzZSAodGh1dGgpCi0gVG9vayB2YXJpb3VzIHBhdGNoZXMgb3V0IHRvIHJlZHVjZSBz ZXJpZXMgKHRodXRoKQotIEFkZGVkIHJldmlldyB0YWdzICh0aGFua3MgYWxsIGZvciByZXZpZXdp bmchKQoKJCBnaXQgYmFja3BvcnQtZGlmZiAtdSBwY19zcGxpdF9pNDQwZnhfcGlpeC12MSAtciBt YzE0NjgxOHJ0Y19pbml0Li4KS2V5OgpbLS0tLV0gOiBwYXRjaGVzIGFyZSBpZGVudGljYWwKWyMj IyNdIDogbnVtYmVyIG9mIGZ1bmN0aW9uYWwgZGlmZmVyZW5jZXMgYmV0d2VlbiB1cHN0cmVhbS9k b3duc3RyZWFtIHBhdGNoCltkb3duXSA6IHBhdGNoIGlzIGRvd25zdHJlYW0tb25seQpUaGUgZmxh Z3MgW0ZDXSBpbmRpY2F0ZSAoRil1bmN0aW9uYWwgYW5kIChDKW9udGV4dHVhbCBkaWZmZXJlbmNl cywgcmVzcGVjdGl2ZWx5CgowMDEvMjA6Wy0tLS1dIFstLV0gJ01BSU5UQUlORVJTOiBLZWVwIFBJ SVg0IFNvdXRoIEJyaWRnZSBzZXBhcmF0ZSBmcm9tIFBDIENoaXBzZXRzJwowMDIvMjA6WzAwMTFd IFtGQ10gJ3BpaXg0OiBhZGQgUmVzZXQgQ29udHJvbCBSZWdpc3RlcicKMDAzLzIwOlswMDE0XSBb RkNdICdwaWl4NDogYWRkIGEgaTgyNTkgaW50ZXJydXB0IGNvbnRyb2xsZXIgYXMgc3BlY2lmaWVk IGluIGRhdGFzaGVldCcKMDA0LzIwOlstLS0tXSBbLS1dICdSZXZlcnQgImlycTogaW50cm9kdWNl IHFlbXVfaXJxX3Byb3h5KCkiJwowMDUvMjA6Wy0tLS1dIFstLV0gJ3BpaXg0OiByZW5hbWUgUElJ WDQgb2JqZWN0IHRvIHBpaXg0LWlzYScKMDA2LzIwOlstLS0tXSBbLUNdICdwaWl4NDogYWRkIGEg aTgyNTcgZG1hIGNvbnRyb2xsZXIgYXMgc3BlY2lmaWVkIGluIGRhdGFzaGVldCcKMDA3LzIwOlst LS0tXSBbLUNdICdwaWl4NDogYWRkIGEgaTgyNTQgcGl0IGNvbnRyb2xsZXIgYXMgc3BlY2lmaWVk IGluIGRhdGFzaGVldCcKMDA4LzIwOlstLS0tXSBbLUNdICdwaWl4NDogYWRkIGEgbWMxNDY4MThy dGMgY29udHJvbGxlciBhcyBzcGVjaWZpZWQgaW4gZGF0YXNoZWV0JwowMDkvMjA6Wy0tLS1dIFst LV0gJ2h3L21pcHMvbWlwc19tYWx0YTogQ3JlYXRlIElERSBoYXJkIGRyaXZlIGFycmF5IGR5bmFt aWNhbGx5JwowMTAvMjA6Wy0tLS1dIFstLV0gJ2h3L21pcHMvbWlwc19tYWx0YTogRXh0cmFjdCB0 aGUgUElJWDQgY3JlYXRpb24gY29kZSBhcyBwaWl4NF9jcmVhdGUoKScKMDExLzIwOlstLS0tXSBb LS1dICdody9pc2EvcGlpeDQ6IE1vdmUgcGlpeDRfY3JlYXRlKCkgdG8gaHcvaXNhL3BpaXg0LmMn CjAxMi8yMDpbLS0tLV0gWy0tXSAnaHcvaTM4NjogUmVtb3ZlIG9ic29sZXRlIExvYWRTdGF0ZUhh bmRsZXI6OmxvYWRfc3RhdGVfb2xkIGhhbmRsZXJzJwowMTMvMjA6Wy0tLS1dIFstLV0gJ2h3L3Bj aS1ob3N0L3BpaXg6IEV4dHJhY3QgcGlpeDNfY3JlYXRlKCknCjAxNC8yMDpbMDAxMF0gW0ZDXSAn aHcvcGNpLWhvc3QvcGlpeDogTW92ZSBSQ1JfSU9QT1JUIHJlZ2lzdGVyIGRlZmluaXRpb24nCjAx NS8yMDpbLS0tLV0gWy0tXSAnaHcvcGNpLWhvc3QvcGlpeDogRGVmaW5lIGFuZCB1c2UgdGhlIFBJ SVggSVJRIFJvdXRlIENvbnRyb2wgUmVnaXN0ZXJzJwowMTYvMjA6Wy0tLS1dIFstLV0gJ2h3L3Bj aS1ob3N0L3BpaXg6IE1vdmUgaTQ0MEZYIGRlY2xhcmF0aW9ucyB0byBody9wY2ktaG9zdC9pNDQw ZnguaCcKMDE3LzIwOlstLS0tXSBbLS1dICdody9wY2ktaG9zdC9waWl4OiBGaXggY29kZSBzdHls ZSBpc3N1ZXMnCjAxOC8yMDpbMDAxMl0gW0ZDXSAnaHcvcGNpLWhvc3QvcGlpeDogRXh0cmFjdCBQ SUlYMyBmdW5jdGlvbnMgdG8gaHcvaXNhL3BpaXgzLmMnCjAxOS8yMDpbLS0tLV0gWy0tXSAnaHcv cGNpLWhvc3Q6IFJlbmFtZSBpbmNvcnJlY3RseSBuYW1lZCAncGlpeCcgYXMgJ2k0NDBmeCcnCjAy MC8yMDpbLS0tLV0gWy1DXSAnaHcvcGNpLWhvc3QvaTQ0MGZ4OiBSZW1vdmUgdGhlIGxhc3QgUElJ WDMgdHJhY2VzJwoKUHJldmlvdXMgY292ZXI6CgpUaGlzIHNlcmllcyBpcyBhIHJld29yayBvZiAi cGlpeDQ6IGNsZWFudXAgYW5kIGltcHJvdmVtZW50cyIgWzFdCmZyb20gSGVydsOpLCBhbmQgbXkg InJlbW92ZSBpMzg2L3BjIGRlcGVuZGVuY3k6IFBJSVggY2xlYW51cCIgWzJdLgoKU3RpbGwgdHJ5 aW5nIHRvIHJlbW92ZSB0aGUgc3Ryb25nIFg4Ni9QQyBkZXBlbmRlbmN5IDIgeWVhcnMgbGF0ZXIs Cm9uZSBzdGVwIGF0IGEgdGltZS4KSGVyZSB3ZSBzcGxpdCB0aGUgUElJWDMgc291dGhicmlkZ2Ug ZnJvbSBpNDQwRlggbm9ydGhicmlkZ2UuClRoZSBpNDQwRlggbm9ydGhicmlkZ2UgaXMgb25seSB1 c2VkIGJ5IHRoZSBQQyBtYWNoaW5lLCB3aGlsZSB0aGUKUElJWCBzb3V0aGJyaWRnZSBpcyBhbHNv IHVzZWQgYnkgdGhlIE1hbHRhIE1JUFMgbWFjaGluZS4KClRoaXMgaXMgYWxzbyBhIHN0ZXAgZm9y d2FyZCB1c2luZyBLQ29uZmlnIHdpdGggdGhlIE1hbHRhIGJvYXJkLgpXaXRob3V0IHRoaXMgc3Bs aXQsIGl0IHdhcyBpbXBvc3NpYmxlIHRvIGNvbXBpbGUgdGhlIE1hbHRhIHdpdGhvdXQKcHVsbGlu ZyB2YXJpb3VzIFg4NiBwaWVjZXMgb2YgY29kZS4KClRoZSBvdmVyYWxsIGRlc2lnbiBjbGVhbnVw IGlzIG5vdCB5ZXQgcGVyZmVjdCwgYnV0IGVub3VnaCB0byBwb3N0CmFzIGEgc2VyaWVzLgoKTm93 IHRoYXQgdGhlIFBJSVgzIGNvZGUgaXMgZXh0cmFjdGVkLCB0aGUgY29kZSBkdXBsaWNhdGlvbiB3 aXRoIHRoZQpQSUlYNCBjaGlwc2V0IGlzIG9idmlvdXMuIE5vdCB3b3J0aCBpbXByb3ZpbmcgZm9y IG5vdyBiZWNhdXNlIGl0Cmlzbid0IGJyb2tlbi4KClswXSBodHRwczovL2xpc3RzLmdudS5vcmcv YXJjaGl2ZS9odG1sL3FlbXUtZGV2ZWwvMjAxOS0xMC9tc2cwMzY4NS5odG1sClsxXSBodHRwczov L3d3dy5tYWlsLWFyY2hpdmUuY29tL3FlbXUtZGV2ZWxAbm9uZ251Lm9yZy9tc2c1MDA3MzcuaHRt bApbMl0gaHR0cHM6Ly93d3cubWFpbC1hcmNoaXZlLmNvbS9xZW11LWRldmVsQG5vbmdudS5vcmcv bXNnNTA0MDgxLmh0bWwKCkJhc2VkLW9uOiA8MjAxOTEwMTgxMzM1NDcuMTA5MzYtMS1waGlsbWRA cmVkaGF0LmNvbT4KbWMxNDY4MThydGM6IEFsbG93IGNhbGwgb2JqZWN0X2luaXRpYWxpemUoTUMx NDY4MThfUlRDKSBpbnN0ZWFkIG9mIHJ0Y19pbml0KCkKaHR0cHM6Ly9taWQubWFpbC1hcmNoaXZl LmNvbS8yMDE5MTAxODEzMzU0Ny4xMDkzNi0xLXBoaWxtZEByZWRoYXQuY29tCgpIZXJ2w6kgUG91 c3NpbmVhdSAoNSk6CiAgcGlpeDQ6IEFkZCB0aGUgUmVzZXQgQ29udHJvbCBSZWdpc3RlcgogIHBp aXg0OiBBZGQgYSBpODI1OSBJbnRlcnJ1cHQgQ29udHJvbGxlciBhcyBzcGVjaWZpZWQgaW4gZGF0 YXNoZWV0CiAgcGlpeDQ6IFJlbmFtZSBQSUlYNCBvYmplY3QgdG8gcGlpeDQtaXNhCiAgcGlpeDQ6 IEFkZCBhIGk4MjU3IERNQSBDb250cm9sbGVyIGFzIHNwZWNpZmllZCBpbiBkYXRhc2hlZXQKICBw aWl4NDogQWRkIGEgaTgyNTQgUElUIENvbnRyb2xsZXIgYXMgc3BlY2lmaWVkIGluIGRhdGFzaGVl dAoKUGhpbGlwcGUgTWF0aGlldS1EYXVkw6kgKDE1KToKICBNQUlOVEFJTkVSUzogS2VlcCBQSUlY NCBTb3V0aCBCcmlkZ2Ugc2VwYXJhdGUgZnJvbSBQQyBDaGlwc2V0cwogIFJldmVydCAiaXJxOiBp bnRyb2R1Y2UgcWVtdV9pcnFfcHJveHkoKSIKICBwaWl4NDogQWRkIGEgTUMxNDY4MTggUlRDIENv bnRyb2xsZXIgYXMgc3BlY2lmaWVkIGluIGRhdGFzaGVldAogIGh3L21pcHMvbWlwc19tYWx0YTog Q3JlYXRlIElERSBoYXJkIGRyaXZlIGFycmF5IGR5bmFtaWNhbGx5CiAgaHcvbWlwcy9taXBzX21h bHRhOiBFeHRyYWN0IHRoZSBQSUlYNCBjcmVhdGlvbiBjb2RlIGFzIHBpaXg0X2NyZWF0ZSgpCiAg aHcvaXNhL3BpaXg0OiBNb3ZlIHBpaXg0X2NyZWF0ZSgpIHRvIGh3L2lzYS9waWl4NC5jCiAgaHcv aTM4NjogUmVtb3ZlIG9ic29sZXRlIExvYWRTdGF0ZUhhbmRsZXI6OmxvYWRfc3RhdGVfb2xkIGhh bmRsZXJzCiAgaHcvcGNpLWhvc3QvcGlpeDogRXh0cmFjdCBwaWl4M19jcmVhdGUoKQogIGh3L3Bj aS1ob3N0L3BpaXg6IE1vdmUgUkNSX0lPUE9SVCByZWdpc3RlciBkZWZpbml0aW9uCiAgaHcvcGNp LWhvc3QvcGlpeDogRGVmaW5lIGFuZCB1c2UgdGhlIFBJSVggSVJRIFJvdXRlIENvbnRyb2wgUmVn aXN0ZXJzCiAgaHcvcGNpLWhvc3QvcGlpeDogTW92ZSBpNDQwRlggZGVjbGFyYXRpb25zIHRvIGh3 L3BjaS1ob3N0L2k0NDBmeC5oCiAgaHcvcGNpLWhvc3QvcGlpeDogRml4IGNvZGUgc3R5bGUgaXNz dWVzCiAgaHcvcGNpLWhvc3QvcGlpeDogRXh0cmFjdCBQSUlYMyBmdW5jdGlvbnMgdG8gaHcvaXNh L3BpaXgzLmMKICBody9wY2ktaG9zdDogUmVuYW1lIGluY29ycmVjdGx5IG5hbWVkICdwaWl4JyBh cyAnaTQ0MGZ4JwogIGh3L3BjaS1ob3N0L2k0NDBmeDogUmVtb3ZlIHRoZSBsYXN0IFBJSVgzIHRy YWNlcwoKIE1BSU5UQUlORVJTICAgICAgICAgICAgICAgICAgICAgIHwgIDE0ICstCiBody9hY3Bp L3BjaWhwLmMgICAgICAgICAgICAgICAgICB8ICAgMiArLQogaHcvYWNwaS9waWl4NC5jICAgICAg ICAgICAgICAgICAgfCAgNDIgKy0tCiBody9jb3JlL2lycS5jICAgICAgICAgICAgICAgICAgICB8 ICAxNCAtCiBody9pMzg2L0tjb25maWcgICAgICAgICAgICAgICAgICB8ICAgMyArLQogaHcvaTM4 Ni9hY3BpLWJ1aWxkLmMgICAgICAgICAgICAgfCAgIDUgKy0KIGh3L2kzODYvcGNfcGlpeC5jICAg ICAgICAgICAgICAgIHwgIDEwICstCiBody9pMzg2L3hlbi94ZW4taHZtLmMgICAgICAgICAgICB8 ICAgNSArLQogaHcvaW50Yy9hcGljX2NvbW1vbi5jICAgICAgICAgICAgfCAgNDkgLS0tLQogaHcv aXNhL0tjb25maWcgICAgICAgICAgICAgICAgICAgfCAgIDQgKwogaHcvaXNhL01ha2VmaWxlLm9i anMgICAgICAgICAgICAgfCAgIDEgKwogaHcvaXNhL3BpaXgzLmMgICAgICAgICAgICAgICAgICAg fCAzOTkgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysKIGh3L2lzYS9waWl4NC5jICAgICAg ICAgICAgICAgICAgIHwgMTUxICsrKysrKysrKystCiBody9taXBzL2d0NjR4eHhfcGNpLmMgICAg ICAgICAgICB8ICAgNSArLQogaHcvbWlwcy9taXBzX21hbHRhLmMgICAgICAgICAgICAgfCAgNDYg Ky0tLQogaHcvcGNpLWhvc3QvS2NvbmZpZyAgICAgICAgICAgICAgfCAgIDMgKy0KIGh3L3BjaS1o b3N0L01ha2VmaWxlLm9ianMgICAgICAgIHwgICAyICstCiBody9wY2ktaG9zdC97cGlpeC5jID0+ IGk0NDBmeC5jfSB8IDQyNCArLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tCiBody90aW1l ci9pODI1NF9jb21tb24uYyAgICAgICAgICB8ICA0MCAtLS0KIGluY2x1ZGUvaHcvYWNwaS9waWl4 NC5oICAgICAgICAgIHwgICA2IC0KIGluY2x1ZGUvaHcvaTM4Ni9wYy5oICAgICAgICAgICAgIHwg IDM3IC0tLQogaW5jbHVkZS9ody9pcnEuaCAgICAgICAgICAgICAgICAgfCAgIDUgLQogaW5jbHVk ZS9ody9pc2EvaXNhLmggICAgICAgICAgICAgfCAgIDIgKwogaW5jbHVkZS9ody9wY2ktaG9zdC9p NDQwZnguaCAgICAgfCAgMzYgKysrCiBpbmNsdWRlL2h3L3NvdXRoYnJpZGdlL3BpaXguaCAgICB8 ICA3NCArKysrKysKIHN0dWJzL3BjaS1ob3N0LXBpaXguYyAgICAgICAgICAgIHwgICAzICstCiAy NiBmaWxlcyBjaGFuZ2VkLCA2OTkgaW5zZXJ0aW9ucygrKSwgNjgzIGRlbGV0aW9ucygtKQogY3Jl YXRlIG1vZGUgMTAwNjQ0IGh3L2lzYS9waWl4My5jCiByZW5hbWUgaHcvcGNpLWhvc3Qve3BpaXgu YyA9PiBpNDQwZnguY30gKDU4JSkKIGRlbGV0ZSBtb2RlIDEwMDY0NCBpbmNsdWRlL2h3L2FjcGkv cGlpeDQuaAogY3JlYXRlIG1vZGUgMTAwNjQ0IGluY2x1ZGUvaHcvcGNpLWhvc3QvaTQ0MGZ4LmgK IGNyZWF0ZSBtb2RlIDEwMDY0NCBpbmNsdWRlL2h3L3NvdXRoYnJpZGdlL3BpaXguaAoKLS0gCjIu MjEuMAoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fClhl bi1kZXZlbCBtYWlsaW5nIGxpc3QKWGVuLWRldmVsQGxpc3RzLnhlbnByb2plY3Qub3JnCmh0dHBz Oi8vbGlzdHMueGVucHJvamVjdC5vcmcvbWFpbG1hbi9saXN0aW5mby94ZW4tZGV2ZWw= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED 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From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge Date: Fri, 18 Oct 2019 15:47:34 +0200 Message-Id: <20191018134754.16362-1-philmd@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.41]); Fri, 18 Oct 2019 13:48:06 +0000 (UTC) Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefano Stabellini , "Michael S. Tsirkin" , Paul Durrant , Paolo Bonzini , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Aleksandar Markovic , Igor Mammedov , Anthony Perard , xen-devel@lists.xenproject.org, Aleksandar Rikalo , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , Eduardo Habkost Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Changes since v1 [0]: - Removed patch reintroducing DO_UPCAST() use (thuth) - Took various patches out to reduce series (thuth) - Added review tags (thanks all for reviewing!) $ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init.. Key: [----] : patches are identical [####] : number of functional differences between upstream/downstream pat= ch [down] : patch is downstream-only The flags [FC] indicate (F)unctional and (C)ontextual differences, respec= tively 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC= Chipsets' 002/20:[0011] [FC] 'piix4: add Reset Control Register' 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as specified = in datasheet' 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"' 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa' 006/20:[----] [-C] 'piix4: add a i8257 dma controller as specified in dat= asheet' 007/20:[----] [-C] 'piix4: add a i8254 pit controller as specified in dat= asheet' 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as specified in d= atasheet' 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array dynam= ically' 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code a= s piix4_create()' 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c' 012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_state= _old handlers' 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()' 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition= ' 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route C= ontrol Registers' 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations to hw/pci-= host/i440fx.h' 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues' 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to hw/isa/p= iix3.c' 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as 'i440= fx'' 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3 traces' Previous cover: This series is a rework of "piix4: cleanup and improvements" [1] from Herv=C3=A9, and my "remove i386/pc dependency: PIIX cleanup" [2]. Still trying to remove the strong X86/PC dependency 2 years later, one step at a time. Here we split the PIIX3 southbridge from i440FX northbridge. The i440FX northbridge is only used by the PC machine, while the PIIX southbridge is also used by the Malta MIPS machine. This is also a step forward using KConfig with the Malta board. Without this split, it was impossible to compile the Malta without pulling various X86 pieces of code. The overall design cleanup is not yet perfect, but enough to post as a series. Now that the PIIX3 code is extracted, the code duplication with the PIIX4 chipset is obvious. Not worth improving for now because it isn't broken. [0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html Based-on: <20191018133547.10936-1-philmd@redhat.com> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of rtc_in= it() https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com Herv=C3=A9 Poussineau (5): piix4: Add the Reset Control Register piix4: Add a i8259 Interrupt Controller as specified in datasheet piix4: Rename PIIX4 object to piix4-isa piix4: Add a i8257 DMA Controller as specified in datasheet piix4: Add a i8254 PIT Controller as specified in datasheet Philippe Mathieu-Daud=C3=A9 (15): MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets Revert "irq: introduce qemu_irq_proxy()" piix4: Add a MC146818 RTC Controller as specified in datasheet hw/mips/mips_malta: Create IDE hard drive array dynamically hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create() hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers hw/pci-host/piix: Extract piix3_create() hw/pci-host/piix: Move RCR_IOPORT register definition hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h hw/pci-host/piix: Fix code style issues hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c hw/pci-host: Rename incorrectly named 'piix' as 'i440fx' hw/pci-host/i440fx: Remove the last PIIX3 traces MAINTAINERS | 14 +- hw/acpi/pcihp.c | 2 +- hw/acpi/piix4.c | 42 +-- hw/core/irq.c | 14 - hw/i386/Kconfig | 3 +- hw/i386/acpi-build.c | 5 +- hw/i386/pc_piix.c | 10 +- hw/i386/xen/xen-hvm.c | 5 +- hw/intc/apic_common.c | 49 ---- hw/isa/Kconfig | 4 + hw/isa/Makefile.objs | 1 + hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++ hw/isa/piix4.c | 151 ++++++++++- hw/mips/gt64xxx_pci.c | 5 +- hw/mips/mips_malta.c | 46 +--- hw/pci-host/Kconfig | 3 +- hw/pci-host/Makefile.objs | 2 +- hw/pci-host/{piix.c =3D> i440fx.c} | 424 +------------------------------ hw/timer/i8254_common.c | 40 --- include/hw/acpi/piix4.h | 6 - include/hw/i386/pc.h | 37 --- include/hw/irq.h | 5 - include/hw/isa/isa.h | 2 + include/hw/pci-host/i440fx.h | 36 +++ include/hw/southbridge/piix.h | 74 ++++++ stubs/pci-host-piix.c | 3 +- 26 files changed, 699 insertions(+), 683 deletions(-) create mode 100644 hw/isa/piix3.c rename hw/pci-host/{piix.c =3D> i440fx.c} (58%) delete mode 100644 include/hw/acpi/piix4.h create mode 100644 include/hw/pci-host/i440fx.h create mode 100644 include/hw/southbridge/piix.h --=20 2.21.0