From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 24 Oct 2019 15:36:14 -0000 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120] helo=us-smtp-1.mimecast.com) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iNf9o-0001YJ-Kk for speck@linutronix.de; Thu, 24 Oct 2019 17:36:13 +0200 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id C08691800DD0 for ; Thu, 24 Oct 2019 15:23:05 +0000 (UTC) Received: from treble (ovpn-121-225.rdu2.redhat.com [10.10.121.225]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 3D7945D9D5 for ; Thu, 24 Oct 2019 15:23:05 +0000 (UTC) Date: Thu, 24 Oct 2019 10:22:57 -0500 From: Josh Poimboeuf Subject: [MODERATED] Re: [PATCH 1/9] TAA 1 Message-ID: <20191024152257.eftdgtffaak6cyvn@treble> References: <845fbeac941c6a5f9f9bf588394497faaa694909.1571905227.git.bp@suse.de> MIME-Version: 1.0 In-Reply-To: <845fbeac941c6a5f9f9bf588394497faaa694909.1571905227.git.bp@suse.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Oct 23, 2019 at 10:45:50AM +0200, speck for Pawan Gupta wrote: > From: Pawan Gupta > Subject: [PATCH 1/9] x86/msr: Add the IA32_TSX_CTRL MSR > > Transactional Synchronization Extensions (TSX) may be used on certain > processors as part of a speculative side channel attack. A microcode > update for existing processors that are vulnerable to this attack will > add a new MSR - IA32_TSX_CTRL to allow the system administrator the > option to disable TSX as one of the possible mitigations. This should clarify that not *all* TAA-vulnerable CPUs will get IA32_TSX_CTRL, instead only the ones which aren't also vulnerable to MDS. > [ Note that future processors that are not vulnerable will also > support the IA32_TSX_CTRL MSR. ] > > Add defines for the new IA32_TSX_CTRL MSR and its bits. > > TSX has two sub-features: > > 1. Restricted Transactional Memory (RTM) is an explicitly-used feature > where new instructions begin and end TSX transactions. > 2. Hardware Lock Elision (HLE) is implicitly used when certain kinds of > "old" style locks are used by software. > > Bit 7 of the IA32_ARCH_CAPABILITIES indicates the presence of the > IA32_TSX_CTRL MSR. > > There are two control bits in IA32_TSX_CTRL MSR: > > Bit 0: When set, it disables the Restricted Transactional Memory (RTM) > sub-feature of TSX (will force all transactions to abort on the > XBEGIN instruction). > > Bit 1: When set, it disables the enumeration of the RTM and HLE feature > (i.e. it will make CPUID(EAX=7).EBX{bit4} and > CPUID(EAX=7).EBX{bit11} read as 0). > > The other TSX sub-feature, Hardware Lock Elision (HLE), is > unconditionally disabled ... by the new microcode ... > but still enumerated as present by > CPUID(EAX=7).EBX{bit4}. ... unless disabled by bit 1 of IA32_TSX_CTRL_MSR. -- Josh