From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (193.142.43.55:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 24 Oct 2019 20:06:16 -0000 Received: from mx2.suse.de ([195.135.220.15] helo=mx1.suse.de) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1iNjN8-0008U4-3b for speck@linutronix.de; Thu, 24 Oct 2019 22:06:15 +0200 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx1.suse.de (Postfix) with ESMTP id 372D4B0BF for ; Thu, 24 Oct 2019 20:06:08 +0000 (UTC) Date: Thu, 24 Oct 2019 22:05:58 +0200 From: Borislav Petkov Subject: [MODERATED] Re: [PATCH 3/9] TAA 3 Message-ID: <20191024200558.GJ14115@zn.tnic> References: <580e02757c3e639bff00fcea830aa46eba46a92f.1571905227.git.bp@suse.de> <6f1ab744-622c-179b-276b-5506b2fd9ae1@citrix.com> <20191024194503.GH14115@zn.tnic> <20191024195959.nvdja4kxlbjrgq24@treble> MIME-Version: 1.0 In-Reply-To: <20191024195959.nvdja4kxlbjrgq24@treble> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Thu, Oct 24, 2019 at 02:59:59PM -0500, speck for Josh Poimboeuf wrote: > But pre-TSX_CTRL CPUs won't reach the above code, because of the > tsx_ctrl_is_supported() check at the beginning of tsx_init(). Yes, pre-TSX_CTRL won't have those CPUID bits cleared because they cannot anyway - MSR is not there. And even if we clear the corresponding X86_FEATURE_ bits, nothing is stopping people from using TSX - they won't query /proc/cpuinfo but CPUID directly. Hell, they can even try the instructions and see if they fault or not, without querying any feature bits. > And post-TSX_CTRL CPUs will have the HLE bit already cleared by > microcode. Yes. In both cases, the X86_FEATURE_* bits mirror what's in CPUID. At least for the two TSX bits: HLE and RTM. --=20 Regards/Gruss, Boris. SUSE Software Solutions Germany GmbH, GF: Felix Imend=C3=B6rffer, HRB 36809, = AG N=C3=BCrnberg --=20