From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix PCH reference clock for FDI on HSW/BDW Date: Fri, 25 Oct 2019 20:24:29 +0300 Message-ID: <20191025172429.GH1208@intel.com> References: <20191022185643.1483-1-ville.syrjala@linux.intel.com> <20191023124450.GA11288@ideak-desk.fi.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-path: Content-Disposition: inline In-Reply-To: <20191023124450.GA11288@ideak-desk.fi.intel.com> Sender: stable-owner@vger.kernel.org To: Imre Deak Cc: intel-gfx@lists.freedesktop.org, Andrija , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Oct 23, 2019 at 03:44:50PM +0300, Imre Deak wrote: > On Tue, Oct 22, 2019 at 09:56:43PM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > The change to skip the PCH reference initialization during fastboot > > did end up breaking FDI. To fix that let's try to do the PCH reference > > init whenever we're disabling a DPLL that was using said reference > > previously. > > > > Cc: stable@vger.kernel.org > > Tested-by: Andrija > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112084 > > Fixes: b16c7ed95caf ("drm/i915: Do not touch the PCH SSC reference if a PLL is using it") > > Signed-off-by: Ville Syrjälä > > Reviewed-by: Imre Deak CI had some bsd fails which are not relevant, so pushed to dinq. Thanks for the review. > > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++----- > > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 15 +++++++++++++++ > > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > > 3 files changed, 23 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > > index 236fdf122e47..da76f794a965 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -9359,7 +9359,6 @@ static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv, > > static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) > > { > > struct intel_encoder *encoder; > > - bool pch_ssc_in_use = false; > > bool has_fdi = false; > > > > for_each_intel_encoder(&dev_priv->drm, encoder) { > > @@ -9387,22 +9386,24 @@ static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) > > * clock hierarchy. That would also allow us to do > > * clock bending finally. > > */ > > + dev_priv->pch_ssc_use = 0; > > + > > if (spll_uses_pch_ssc(dev_priv)) { > > DRM_DEBUG_KMS("SPLL using PCH SSC\n"); > > - pch_ssc_in_use = true; > > + dev_priv->pch_ssc_use |= BIT(DPLL_ID_SPLL); > > } > > > > if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL1)) { > > DRM_DEBUG_KMS("WRPLL1 using PCH SSC\n"); > > - pch_ssc_in_use = true; > > + dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL1); > > } > > > > if (wrpll_uses_pch_ssc(dev_priv, DPLL_ID_WRPLL2)) { > > DRM_DEBUG_KMS("WRPLL2 using PCH SSC\n"); > > - pch_ssc_in_use = true; > > + dev_priv->pch_ssc_use |= BIT(DPLL_ID_WRPLL2); > > } > > > > - if (pch_ssc_in_use) > > + if (dev_priv->pch_ssc_use) > > return; > > > > if (has_fdi) { > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > index ec10fa7d3c69..3ce0a023eee0 100644 > > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > > @@ -526,16 +526,31 @@ static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv, > > val = I915_READ(WRPLL_CTL(id)); > > I915_WRITE(WRPLL_CTL(id), val & ~WRPLL_PLL_ENABLE); > > POSTING_READ(WRPLL_CTL(id)); > > + > > + /* > > + * Try to set up the PCH reference clock once all DPLLs > > + * that depend on it have been shut down. > > + */ > > + if (dev_priv->pch_ssc_use & BIT(id)) > > + intel_init_pch_refclk(dev_priv); > > } > > > > static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv, > > struct intel_shared_dpll *pll) > > { > > + enum intel_dpll_id id = pll->info->id; > > u32 val; > > > > val = I915_READ(SPLL_CTL); > > I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); > > POSTING_READ(SPLL_CTL); > > + > > + /* > > + * Try to set up the PCH reference clock once all DPLLs > > + * that depend on it have been shut down. > > + */ > > + if (dev_priv->pch_ssc_use & BIT(id)) > > + intel_init_pch_refclk(dev_priv); > > } > > > > static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv, > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > > index 8882c0908c3b..5332825e0ce4 100644 > > --- a/drivers/gpu/drm/i915/i915_drv.h > > +++ b/drivers/gpu/drm/i915/i915_drv.h > > @@ -1348,6 +1348,8 @@ struct drm_i915_private { > > } contexts; > > } gem; > > > > + u8 pch_ssc_use; > > + > > /* For i915gm/i945gm vblank irq workaround */ > > u8 vblank_enabled; > > > > -- > > 2.21.0 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19F2ECA9EBD for ; Fri, 25 Oct 2019 17:24:35 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E76B621872 for ; Fri, 25 Oct 2019 17:24:34 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E76B621872 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 62B4B6EB09; Fri, 25 Oct 2019 17:24:34 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id C41546EB09 for ; Fri, 25 Oct 2019 17:24:32 +0000 (UTC) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2019 10:24:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,229,1569308400"; d="scan'208";a="228974992" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga002.fm.intel.com with SMTP; 25 Oct 2019 10:24:29 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 25 Oct 2019 20:24:29 +0300 Date: Fri, 25 Oct 2019 20:24:29 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Imre Deak Message-ID: <20191025172429.GH1208@intel.com> References: <20191022185643.1483-1-ville.syrjala@linux.intel.com> <20191023124450.GA11288@ideak-desk.fi.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191023124450.GA11288@ideak-desk.fi.intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix PCH reference clock for FDI on HSW/BDW X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org, stable@vger.kernel.org, Andrija Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Message-ID: <20191025172429.ypM38faaOfZCFjZAJXfZQyB0-t30k9-2Bl9WHhFVwtY@z> T24gV2VkLCBPY3QgMjMsIDIwMTkgYXQgMDM6NDQ6NTBQTSArMDMwMCwgSW1yZSBEZWFrIHdyb3Rl Ogo+IE9uIFR1ZSwgT2N0IDIyLCAyMDE5IGF0IDA5OjU2OjQzUE0gKzAzMDAsIFZpbGxlIFN5cmph bGEgd3JvdGU6Cj4gPiBGcm9tOiBWaWxsZSBTeXJqw6Rsw6QgPHZpbGxlLnN5cmphbGFAbGludXgu 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