From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAA1ECA9EC4 for ; Tue, 29 Oct 2019 21:38:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id ACAFE20717 for ; Tue, 29 Oct 2019 21:38:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1572385080; bh=rbmUINasJZJd0GwJsXJu9ipOl8vcXmbvjndpiAJJQxk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:List-ID:From; b=Ltqq3wB0QuLZFyp4bgBPUWtszI4/kA0yFyD+Wg/OOGysi1KLhmhP3DideAf/Yv9Bp 1LcuQ96tpPUZRoZUSWlY4Gqv0UK1Dhh03EoctOpLOGTlPGGIDKa/V8kEdT1PImkhUX 1LEZuk6QvGVH4AWsQtVusmuuNGGODpKkCx53/0Qk= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728549AbfJ2ViA (ORCPT ); Tue, 29 Oct 2019 17:38:00 -0400 Received: from mail-ot1-f68.google.com ([209.85.210.68]:36359 "EHLO mail-ot1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727706AbfJ2ViA (ORCPT ); Tue, 29 Oct 2019 17:38:00 -0400 Received: by mail-ot1-f68.google.com with SMTP id c7so269535otm.3; Tue, 29 Oct 2019 14:37:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=HPk/5F3b4dwjuAgfQmnttu0kTaOON9LgkQM/V749G3U=; b=ldPZRMNoOEsvxQSLrVsZsB2vaAyJMN9JWGghaVvDXtP4u5ecCVsnf9cPa9MCHgY3BD RCVqiSfQJBvo8gHGyuSjeI4SNGjY7AMEvUyW10N2dveXWgnmuFdNr33NMsI7ZbKug887 Zc18rEx44urVurPllxdsBjOghfg4v4VyCauNZ41bGId/hgY6zXznaqk8t61vAmWFqNYR CYyaSEDel0TJa+yntGZeQjxuC4HT/vJcTMdNsEEHVI5fdKXh1w8WjYXUgXY+JZu+Sio4 fgzFJX/l3obqAL2l+bR8+zC/4Vl6T+WnaMBdDERRjmA/N3k7phxdnDNQAW8u27cYAudt Sn4g== X-Gm-Message-State: APjAAAVRR4xeZRZ+w8Cwf+Jyi/hgYlWXPEY4UW07hIekiVGg/kNpAto2 6u5Uv3FPgJ/FCIYU+ULOSw== X-Google-Smtp-Source: APXvYqy7vhLoX8SU0VKqi+P/9oYgBPX9zkqE7WV/iDYFf8wu0E5QI6Ui9HTTqSZxoCU6ChBhHps5bQ== X-Received: by 2002:a9d:6655:: with SMTP id q21mr16322722otm.47.1572385079003; Tue, 29 Oct 2019 14:37:59 -0700 (PDT) Received: from localhost (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id k10sm4175oig.25.2019.10.29.14.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 14:37:58 -0700 (PDT) Date: Tue, 29 Oct 2019 16:37:57 -0500 From: Rob Herring To: Codrin Ciubotariu Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ludovic.desroches@microchip.com, linus.walleij@linaro.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, claudiu.beznea@microchip.com Subject: Re: [PATCH] pinctrl: at91: Enable slewrate by default on SAM9X60 Message-ID: <20191029213757.GA8829@bogus> References: <20191024172234.5267-1-codrin.ciubotariu@microchip.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191024172234.5267-1-codrin.ciubotariu@microchip.com> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Thu, Oct 24, 2019 at 08:22:34PM +0300, Codrin Ciubotariu wrote: > On SAM9X60, slewrate should be enabled on pins with a switching frequency > below 50Mhz. Since most of our pins do not exceed this value, we enable > slewrate by default. Pins with a switching value that exceeds 50Mhz will > have to explicitly disable slewrate. > > Suggested-by: Ludovic Desroches > Signed-off-by: Codrin Ciubotariu > --- > drivers/pinctrl/pinctrl-at91.c | 4 ++-- > include/dt-bindings/pinctrl/at91.h | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c > index 117075b5798f..c135149e84e9 100644 > --- a/drivers/pinctrl/pinctrl-at91.c > +++ b/drivers/pinctrl/pinctrl-at91.c > @@ -85,8 +85,8 @@ enum drive_strength_bit { > DRIVE_STRENGTH_SHIFT) > > enum slewrate_bit { > - SLEWRATE_BIT_DIS, > SLEWRATE_BIT_ENA, > + SLEWRATE_BIT_DIS, > }; > > #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT) > @@ -669,7 +669,7 @@ static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, > { > unsigned int tmp; > > - if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA) > + if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS) > return; > > tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); > diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h > index 3831f91fb3ba..e8e117306b1b 100644 > --- a/include/dt-bindings/pinctrl/at91.h > +++ b/include/dt-bindings/pinctrl/at91.h > @@ -27,8 +27,8 @@ > #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) > #define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) > > -#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9) > -#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9) > +#define AT91_PINCTRL_SLEWRATE_ENA (0x0 << 9) > +#define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9) This is an ABI. You can't just change the definition. Rob From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 767A2CA9EAE for ; Tue, 29 Oct 2019 21:38:04 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 45E8F21479 for ; Tue, 29 Oct 2019 21:38:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="j2r3e/p3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 45E8F21479 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=yW3IFwsZf5WxdTefo1apBk0agOzdM3bet3XO6Gb9VDQ=; b=j2r3e/p3d7M7aX bv0cgfE5BrH0LGJEra8RNp7z+6f7y+HStJx7A68ie/3PS7gsQfPT6I6DT9FUeFWW9M+enyfJ2VIUd IC4a5p7TTruXSpZwgcvfMiL176kICLP4TdAlCjSSYMMZttC1EJP78UNhhQISukKNPw4ZcUfrAdJdc xaedCQiwoghvGZ7KQ1O8JnApYQ8vw8puiTeRWNK5hNdDXAMh0OtdtVKHtcykAggfgZuNmr8Xf2G0m CP6DpKewu79jHrNT8MAYvW1rRqSIevBUUX0T5KNiYOJlw5ObWpL7xgdTzip+/OaZ9lnkmgBJDRbnr YbbkSSMQEIjxe7gQ2+9Q==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1iPZBj-0003qm-LP; Tue, 29 Oct 2019 21:38:03 +0000 Received: from mail-ot1-f65.google.com ([209.85.210.65]) by bombadil.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1iPZBg-0003pp-57 for linux-arm-kernel@lists.infradead.org; Tue, 29 Oct 2019 21:38:01 +0000 Received: by mail-ot1-f65.google.com with SMTP id b16so239923otk.9 for ; Tue, 29 Oct 2019 14:37:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=HPk/5F3b4dwjuAgfQmnttu0kTaOON9LgkQM/V749G3U=; b=FFbbCkhiKJ24/WZTGqjwvy+LbSL2ovnfi8E0r7aAMhPcLRFwvTfBvju8SlabnUAK49 +8SkIYoMDdDgoR8zLS9odNQG2x/uBvDAeddwEZ7+EaA4qY8vuU5cxoZ5locnVbqawdUO AwMYu18+XYieSsqbadE7xsAfcC0wOC9U3sJX8WcOVvgjdrMAIpcopXQj373+AUlknUmP bCWkImnLVHpIUGUMQkob4dx5knDYCSTEH8N1pwoybYN/EYzERT6eJhCSBatRb6i1Z38p f/lnRZHHWqf0uG2Pi4XKw4zzzvL7Ns21XVAq0incr8Eu/wtaboYV4MhhekTPesAxhunO TkSg== X-Gm-Message-State: APjAAAWmb3j5a1JBy/OEoEkE9/rJyrqmUSubqmJh8P2CscJzBRV/H4TA PPAVSsd1T7IXIt4h1GGb4g== X-Google-Smtp-Source: APXvYqy7vhLoX8SU0VKqi+P/9oYgBPX9zkqE7WV/iDYFf8wu0E5QI6Ui9HTTqSZxoCU6ChBhHps5bQ== X-Received: by 2002:a9d:6655:: with SMTP id q21mr16322722otm.47.1572385079003; Tue, 29 Oct 2019 14:37:59 -0700 (PDT) Received: from localhost (24-155-109-49.dyn.grandenetworks.net. [24.155.109.49]) by smtp.gmail.com with ESMTPSA id k10sm4175oig.25.2019.10.29.14.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 14:37:58 -0700 (PDT) Date: Tue, 29 Oct 2019 16:37:57 -0500 From: Rob Herring To: Codrin Ciubotariu Subject: Re: [PATCH] pinctrl: at91: Enable slewrate by default on SAM9X60 Message-ID: <20191029213757.GA8829@bogus> References: <20191024172234.5267-1-codrin.ciubotariu@microchip.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191024172234.5267-1-codrin.ciubotariu@microchip.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191029_143800_197059_427C402E X-CRM114-Status: GOOD ( 14.92 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, alexandre.belloni@bootlin.com, linus.walleij@linaro.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, ludovic.desroches@microchip.com, claudiu.beznea@microchip.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 24, 2019 at 08:22:34PM +0300, Codrin Ciubotariu wrote: > On SAM9X60, slewrate should be enabled on pins with a switching frequency > below 50Mhz. Since most of our pins do not exceed this value, we enable > slewrate by default. Pins with a switching value that exceeds 50Mhz will > have to explicitly disable slewrate. > > Suggested-by: Ludovic Desroches > Signed-off-by: Codrin Ciubotariu > --- > drivers/pinctrl/pinctrl-at91.c | 4 ++-- > include/dt-bindings/pinctrl/at91.h | 4 ++-- > 2 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c > index 117075b5798f..c135149e84e9 100644 > --- a/drivers/pinctrl/pinctrl-at91.c > +++ b/drivers/pinctrl/pinctrl-at91.c > @@ -85,8 +85,8 @@ enum drive_strength_bit { > DRIVE_STRENGTH_SHIFT) > > enum slewrate_bit { > - SLEWRATE_BIT_DIS, > SLEWRATE_BIT_ENA, > + SLEWRATE_BIT_DIS, > }; > > #define SLEWRATE_BIT_MSK(name) (SLEWRATE_BIT_##name << SLEWRATE_SHIFT) > @@ -669,7 +669,7 @@ static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, > { > unsigned int tmp; > > - if (setting < SLEWRATE_BIT_DIS || setting > SLEWRATE_BIT_ENA) > + if (setting < SLEWRATE_BIT_ENA || setting > SLEWRATE_BIT_DIS) > return; > > tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); > diff --git a/include/dt-bindings/pinctrl/at91.h b/include/dt-bindings/pinctrl/at91.h > index 3831f91fb3ba..e8e117306b1b 100644 > --- a/include/dt-bindings/pinctrl/at91.h > +++ b/include/dt-bindings/pinctrl/at91.h > @@ -27,8 +27,8 @@ > #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) > #define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) > > -#define AT91_PINCTRL_SLEWRATE_DIS (0x0 << 9) > -#define AT91_PINCTRL_SLEWRATE_ENA (0x1 << 9) > +#define AT91_PINCTRL_SLEWRATE_ENA (0x0 << 9) > +#define AT91_PINCTRL_SLEWRATE_DIS (0x1 << 9) This is an ABI. You can't just change the definition. Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel