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[94.29.10.250]) by smtp.gmail.com with ESMTPSA id c24sm553812lfm.20.2019.10.30.14.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2019 14:35:22 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , "Rafael J. Wysocki" , Viresh Kumar , Michael Turquette , Stephen Boyd , Peter Geis , Nicolas Chauvet , Marcel Ziswiler Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 00/10] NVIDIA Tegra20 CPUFreq driver major update Date: Thu, 31 Oct 2019 00:33:50 +0300 Message-Id: <20191030213400.29434-1-digetx@gmail.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Hello, This series moves intermediate-clk handling from tegra20-cpufreq into tegra-clk driver. This allows us to switch to generic cpufreq-dt driver which brings voltage scaling, per-hardware OPPs and Tegra30 support out of the box. All boards need to adopt CPU OPPs in their device-trees in order to get cpufreq support. Changelog: v3: - The "Add custom CCLK implementation" patch was updated in accordance to the comments from Peter De Schrijver. We will not use the clock skipper. - Re added OPPs for T30 Beaver board because Thierry has that board ;) - Added r-b for the "DT binding" patch from Rob Herring. v2: - Kept modularity of the tegra20-cpufreq as was requested by Viresh Kumar in a review comment to v1. - Added acks from Viresh Kumar. - Added tested-by from Nicolas Chauvet to the "trimslice" patch. Nicolas told me on IRC that it works fine. - Fixed compilation of the "Add custom CCLK implementation" patch. The error happened because v1 was based on top of yet unreviewed/unapplied patch "clk: tegra: divider: Support enable-bit for Super clocks". Thanks to Peter Geis for reporting the problem. - Replaced Tegra30 "beaver" board with "cardhu-a04" because turned out that's what NVIDIA uses in the testing farm. Dmitry Osipenko (10): clk: tegra: Add custom CCLK implementation clk: tegra: pll: Add pre/post rate-change hooks clk: tegra: cclk: Add helpers for handling PLLX rate changes clk: tegra20: Support custom CCLK implementation clk: tegra30: Support custom CCLK implementation dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS ARM: dts: tegra30: beaver: Add CPU Operating Performance Points .../cpufreq/nvidia,tegra20-cpufreq.txt | 56 +++++ arch/arm/boot/dts/tegra30-beaver.dts | 40 +++- arch/arm/mach-tegra/tegra.c | 4 + drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-pll.c | 12 +- drivers/clk/tegra/clk-tegra-super-cclk.c | 210 +++++++++++++++++ drivers/clk/tegra/clk-tegra20.c | 7 +- drivers/clk/tegra/clk-tegra30.c | 6 +- drivers/clk/tegra/clk.h | 19 +- drivers/cpufreq/Kconfig.arm | 6 +- drivers/cpufreq/cpufreq-dt-platdev.c | 2 + drivers/cpufreq/tegra20-cpufreq.c | 211 +++++------------- 12 files changed, 400 insertions(+), 174 deletions(-) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c -- 2.23.0