From: Stephen Boyd <sboyd@kernel.org>
To: Dmitry Osipenko <digetx@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Thierry Reding <thierry.reding@gmail.com>
Cc: linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
Date: Wed, 13 Nov 2019 15:03:01 -0800 [thread overview]
Message-ID: <20191113230303.726AE206E3@mail.kernel.org> (raw)
In-Reply-To: <20191030004813.9187-1-digetx@gmail.com>
Quoting Dmitry Osipenko (2019-10-29 17:48:13)
> UART clock is divided using divisor values from DLM/DLL registers when
> enable-bit is unset in clk register and clk's divider configuration isn't
> taken onto account in this case. This doesn't cause any problems, but
> let's add a check for the divider's enable-bit state, for consistency.
>
> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
Is this going to be picked up or should I just apply atop the tegra PR?
next prev parent reply other threads:[~2019-11-13 23:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-30 0:48 [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation Dmitry Osipenko
2019-11-13 23:03 ` Stephen Boyd [this message]
2019-11-14 11:29 ` Dmitry Osipenko
2019-11-14 11:56 ` Thierry Reding
2019-11-14 12:10 ` Dmitry Osipenko
2019-11-15 21:36 ` Stephen Boyd
2019-11-14 11:54 ` Thierry Reding
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