From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Anil Varughese <aniljoy@cadence.com>,
Roger Quadros <rogerq@ti.com>, Jyri Sarha <jsarha@ti.com>
Cc: <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: [PATCH v3 08/14] phy: cadence: Sierra: Get reset control "array" for each link
Date: Thu, 28 Nov 2019 16:16:42 +0530 [thread overview]
Message-ID: <20191128104648.21894-9-kishon@ti.com> (raw)
In-Reply-To: <20191128104648.21894-1-kishon@ti.com>
A link may have multiple lanes each with a separate reset. Get
reset control "array" in order to reset all the lanes associated
with the link.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index fdca3bd178c6..497c83827670 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -499,7 +499,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
struct phy *gphy;
sp->phys[node].lnk_rst =
- of_reset_control_get_exclusive_by_index(child, 0);
+ of_reset_control_array_get_exclusive(child);
if (IS_ERR(sp->phys[node].lnk_rst)) {
dev_err(dev, "failed to get reset %s\n",
--
2.17.1
next prev parent reply other threads:[~2019-11-28 10:48 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-28 10:46 [PATCH v3 00/14] PHY: Add support for SERDES in TI's J721E SoC Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 01/14] dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E Kishon Vijay Abraham I
2019-12-13 20:54 ` Rob Herring
2019-11-28 10:46 ` [PATCH v3 02/14] phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 03/14] phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 04/14] phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 05/14] phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 06/14] phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 07/14] phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Kishon Vijay Abraham I
2019-11-28 10:46 ` Kishon Vijay Abraham I [this message]
2019-11-28 10:46 ` [PATCH v3 09/14] phy: cadence: Sierra: Check for PLL lock during PHY power on Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 10/14] phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 11/14] phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 12/14] phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings Kishon Vijay Abraham I
2019-12-13 21:01 ` Rob Herring
2019-12-16 9:55 ` Kishon Vijay Abraham I
2019-11-28 10:46 ` [PATCH v3 14/14] phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC Kishon Vijay Abraham I
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