From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3931DC43603 for ; Fri, 13 Dec 2019 01:16:43 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 13C0A2173E for ; Fri, 13 Dec 2019 01:16:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 13C0A2173E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9A1376E237; Fri, 13 Dec 2019 01:16:42 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id EE75A6E237 for ; Fri, 13 Dec 2019 01:16:41 +0000 (UTC) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Dec 2019 17:16:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,307,1571727600"; d="scan'208";a="415476819" Received: from labuser-z97x-ud5h.jf.intel.com (HELO intel.com) ([10.54.75.49]) by fmsmga006.fm.intel.com with ESMTP; 12 Dec 2019 17:16:40 -0800 Date: Thu, 12 Dec 2019 17:18:02 -0800 From: Manasi Navare To: Matt Roper Message-ID: <20191213011802.GF24342@intel.com> References: <20191211211425.17821-1-manasi.d.navare@intel.com> <20191211211425.17821-2-manasi.d.navare@intel.com> <20191213003232.GR85422@mdroper-desk1.amr.corp.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191213003232.GR85422@mdroper-desk1.amr.corp.intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/dp: Make sure all tiled connectors get added to the state with full modeset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, Dec 12, 2019 at 04:32:32PM -0800, Matt Roper wrote: > On Wed, Dec 11, 2019 at 01:14:23PM -0800, Manasi Navare wrote: > > In case of tiled displays, all the tiles are linke dto each other > = > Minor typo on "linked to" here. I will fix it > = > > for transcoder port sync. So in intel_atomic_check() we need to make > > sure that we add all the tiles to the modeset and if one of the > > tiles needs a full modeset then mark all other tiles for a full modeset. > > = > > Suggested-by: Ville Syrj=E4l=E4 > > Cc: Ville Syrj=E4l=E4 > > Cc: Jos=E9 Roberto de Souza > > Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5 > = > I think we're moving to "Closes:" as the annotation here now that it's > not actually a bugzilla bug database anymore. Ok cool, will change that to Closes > = > > Signed-off-by: Manasi Navare > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 78 ++++++++++++++++++++ > > 1 file changed, 78 insertions(+) > > = > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu= /drm/i915/display/intel_display.c > > index 803993a01ca7..7263eaa66cda 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -14066,6 +14066,80 @@ static int intel_atomic_check_crtcs(struct int= el_atomic_state *state) > > return 0; > > } > > = > > +static int > > +intel_dp_modeset_all_tiles(struct drm_i915_private *dev_priv, > > + struct intel_atomic_state *state, int tile_grp_id) > > +{ > > + struct drm_connector *conn_iter; > > + struct drm_connector_list_iter conn_list_iter; > > + struct drm_crtc_state *crtc_state; > > + > > + drm_connector_list_iter_begin(&dev_priv->drm, &conn_list_iter); > > + drm_for_each_connector_iter(conn_iter, &conn_list_iter) { > > + struct drm_connector_state *conn_iter_state; > > + > > + if (!conn_iter->has_tile) > > + continue; > > + conn_iter_state =3D drm_atomic_get_connector_state(&state->base, > > + conn_iter); > > + if (IS_ERR(conn_iter_state)) { > > + drm_connector_list_iter_end(&conn_list_iter); > > + return PTR_ERR(conn_iter_state); > > + } > > + > > + if (!conn_iter_state->crtc) > > + continue; > > + > > + if (conn_iter->tile_group->id !=3D tile_grp_id) > > + continue; > > + > > + crtc_state =3D drm_atomic_get_crtc_state(&state->base, conn_iter_sta= te->crtc); > > + if (IS_ERR(crtc_state)) { > > + drm_connector_list_iter_end(&conn_list_iter); > > + return PTR_ERR(conn_iter_state); > > + } > > + crtc_state->mode_changed =3D true; > > + } > > + drm_connector_list_iter_end(&conn_list_iter); > > + > > + return 0; > > +} > > + > > +static int > > +intel_dp_atomic_trans_port_sync_check(struct drm_i915_private *dev_pri= v, > > + struct intel_atomic_state *state) > > +{ > > + struct drm_connector *connector; > > + struct drm_crtc_state *crtc_state; > > + struct drm_connector_state *connector_state; > > + int i, ret, tile_grp_id =3D 0; > > + > > + if (INTEL_GEN(dev_priv) < 11) > > + return 0; > > + > > + /* Is tiled, mark all other tiled CRTCs as needing a modeset */ > > + for_each_new_connector_in_state(&state->base, connector, connector_st= ate, i) { > > + if (!connector->has_tile) > > + continue; > > + if (connector_state->crtc && > > + tile_grp_id !=3D connector->tile_group->id) { > > + crtc_state =3D drm_atomic_get_new_crtc_state(&state->base, > > + connector_state->crtc); > > + if (!drm_atomic_crtc_needs_modeset(crtc_state)) > > + continue; > > + > > + tile_grp_id =3D connector->tile_group->id; > > + } else > = > Minor kernel coding style violation; if we use {} on one branch of an > if, we need to use them on all. > Yes i got a checkpatch check warning, will fix it = > > + continue; > > + > > + ret =3D intel_dp_modeset_all_tiles(dev_priv, state, tile_grp_id); > > + if (ret) > > + return ret; > > + } > > + > > + return 0; > > +} > > + > > /** > > * intel_atomic_check - validate state object > > * @dev: drm device > > @@ -14093,6 +14167,10 @@ static int intel_atomic_check(struct drm_devic= e *dev, > > if (ret) > > goto fail; > > = > > + ret =3D intel_dp_atomic_trans_port_sync_check(dev_priv, state); > > + if (ret) > > + goto fail; > = > Should this happen before the drm_atomic_helper_check_modeset() just > above (or should we re-call that function if we flag the other tile as > needing a modeset)? The kerneldoc on that function says: > = > """ > Drivers which set &drm_crtc_state.mode_changed [...] _must_ call this > function afterwards after that change. It is permitted to call this > function multiple times for the same update ... > """ > IMO, here infact it makes sense to call my function after the drm_atomic_he= lper_check_modeset() because it directly sets the new_crtc_state->mode_changed to true for all t= iles if 1 of them needs a full modeset. And whether that one tile needs a full modeset or not will be decided based= on mode changed for that set in drm_atomic_helper_check_modeset. Manasi = > = > Matt > = > > + > > for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, > > new_crtc_state, i) { > > if (!needs_modeset(new_crtc_state)) { > > -- = > > 2.19.1 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Matt Roper > Graphics Software Engineer > VTT-OSGC Platform Enablement > Intel Corporation > (916) 356-2795 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx