From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id F0423C341CF for ; Fri, 13 Dec 2019 20:38:52 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 409CF246B1 for ; Fri, 13 Dec 2019 20:38:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 409CF246B1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 485946EDB7; Fri, 13 Dec 2019 20:38:51 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D5C06EDB7 for ; Fri, 13 Dec 2019 20:38:50 +0000 (UTC) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Dec 2019 12:38:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,311,1571727600"; d="scan'208";a="211547576" Received: from labuser-z97x-ud5h.jf.intel.com (HELO intel.com) ([10.54.75.49]) by fmsmga008.fm.intel.com with ESMTP; 13 Dec 2019 12:38:49 -0800 Date: Fri, 13 Dec 2019 12:40:13 -0800 From: Manasi Navare To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Message-ID: <20191213204012.GE19224@intel.com> References: <20191211211425.17821-1-manasi.d.navare@intel.com> <20191211211425.17821-4-manasi.d.navare@intel.com> <20191213200637.GE1208@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191213200637.GE1208@intel.com> User-Agent: Mutt/1.5.24 (2015-08-30) Subject: Re: [Intel-gfx] [PATCH 3/3] drm/i915/dp: Disable Port sync mode correctly on teardown X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , intel-gfx@lists.freedesktop.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, Dec 13, 2019 at 10:06:37PM +0200, Ville Syrj=E4l=E4 wrote: > On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote: > > While clearing the Ports ync mode enable and master select bits > > we need to make sure that we perform a RMW for disable else > > it sets the other bits casuing unwanted sideeffects. > > = > > Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5 > > Cc: Ville Syrj=E4l=E4 > > Cc: Jani Nikula > > Fixes: 51528afe7c5e ("drm/i915/display/icl: Disable transcoder port syn= c as part of crtc_disable() sequence") > > Signed-off-by: Manasi Navare > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > = > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu= /drm/i915/display/intel_display.c > > index c0a2dab3fe67..3fccda0f1f36 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -4599,7 +4599,8 @@ static void icl_disable_transcoder_port_sync(cons= t struct intel_crtc_state *old_ > > transcoder_name(old_crtc_state->cpu_transcoder)); > > = > > reg =3D TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder); > > - trans_ddi_func_ctl2_val =3D ~(PORT_SYNC_MODE_ENABLE | > > + trans_ddi_func_ctl2_val =3D I915_READ(reg); > > + trans_ddi_func_ctl2_val &=3D ~(PORT_SYNC_MODE_ENABLE | > > PORT_SYNC_MODE_MASTER_SELECT_MASK); > > I915_WRITE(reg, trans_ddi_func_ctl2_val); > = > I915_WRITE(TRANS_DDI_FUNC_CTL2, 0); So not even consider the other values that might have been set in this reg? You would prefer setting this to 0 directly? Right now i do see that no other bits are set, but things can change when we start using DSI port sync mode or genlock mode etc. Manasi > = > > } > > -- = > > 2.19.1 > = > -- = > Ville Syrj=E4l=E4 > Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx