From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Imre Deak <imre.deak@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [Intel-gfx] [PATCH 05/15] drm/i915: Add helpers to select correct ccs/aux planes
Date: Fri, 20 Dec 2019 16:03:20 +0200 [thread overview]
Message-ID: <20191220140320.GM1208@intel.com> (raw)
In-Reply-To: <20191220002607.GB8384@ideak-desk.fi.intel.com>
On Fri, Dec 20, 2019 at 02:26:07AM +0200, Imre Deak wrote:
> On Thu, Dec 19, 2019 at 01:04:33PM -0800, Matt Roper wrote:
> > On Wed, Dec 18, 2019 at 06:10:55PM +0200, Imre Deak wrote:
> > > Using helpers instead of open coding this to select a CCS plane for a
> > > main plane makes the code cleaner and less error-prone when the location
> > > of CCS plane can be different based on the format (packed vs. YUV
> > > semiplanar). The same applies to selecting an AUX plane which can be a
> > > UV plane (for an uncompressed YUV semiplanar format), or a CCS plane.
> > >
> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> >
> > Looking at this makes me wonder if some of the aux stuff that we're
> > doing for YUV in skl_check_main_surface is actually necessary for gen11+
> > now that we have separate planes rather than an AUX surface in the same
> > plane.
>
> I also wondered if programming the UV surface's offset in the Y plane's
> AUX_DIST register is necessary or not on GEN11+, however that's what we
> do atm.
Shouldn't be needed. But I presume you're changing that anyway for media
compression since you need aux for both Y and UV?
>
> >
> > But none of the logic should be impacted by your changes here so,
> >
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> >
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 63 ++++++++++++++++----
> > > 1 file changed, 50 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index 4b8b44c39724..6bda397ae677 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -1933,6 +1933,40 @@ static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
> > > return IS_GEN(dev_priv, 2) ? 2048 : 4096;
> > > }
> > >
> > > +static bool is_ccs_plane(const struct drm_framebuffer *fb, int plane)
> > > +{
> > > + if (!is_ccs_modifier(fb->modifier))
> > > + return false;
> > > +
> > > + return plane >= fb->format->num_planes / 2;
> > > +}
> > > +
> > > +static bool is_aux_plane(const struct drm_framebuffer *fb, int plane)
> > > +{
> > > + if (is_ccs_modifier(fb->modifier))
> > > + return is_ccs_plane(fb, plane);
> > > +
> > > + return plane == 1;
> > > +}
> > > +
> > > +static int main_to_ccs_plane(const struct drm_framebuffer *fb, int main_plane)
> > > +{
> > > + WARN_ON(!is_ccs_modifier(fb->modifier) ||
> > > + (main_plane && main_plane >= fb->format->num_planes / 2));
> > > +
> > > + return fb->format->num_planes / 2 + main_plane;
> > > +}
> > > +
> > > +/* Return either the main plane's CCS or - if not a CCS FB - UV plane */
> > > +static int
> > > +intel_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
> > > +{
> > > + if (is_ccs_modifier(fb->modifier))
> > > + return main_to_ccs_plane(fb, main_plane);
> > > +
> > > + return 1;
> > > +}
> > > +
> > > static unsigned int
> > > intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > {
> > > @@ -1948,7 +1982,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > else
> > > return 512;
> > > case I915_FORMAT_MOD_Y_TILED_CCS:
> > > - if (color_plane == 1)
> > > + if (is_ccs_plane(fb, color_plane))
> > > return 128;
> > > /* fall through */
> > > case I915_FORMAT_MOD_Y_TILED:
> > > @@ -1957,7 +1991,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> > > else
> > > return 512;
> > > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > > - if (color_plane == 1)
> > > + if (is_ccs_plane(fb, color_plane))
> > > return 128;
> > > /* fall through */
> > > case I915_FORMAT_MOD_Yf_TILED:
> > > @@ -2074,7 +2108,7 @@ static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> > > struct drm_i915_private *dev_priv = to_i915(fb->dev);
> > >
> > > /* AUX_DIST needs only 4K alignment */
> > > - if (color_plane == 1)
> > > + if (is_aux_plane(fb, color_plane))
> > > return 4096;
> > >
> > > switch (fb->modifier) {
> > > @@ -3457,10 +3491,11 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> > > const struct drm_framebuffer *fb = plane_state->hw.fb;
> > > int hsub = fb->format->hsub;
> > > int vsub = fb->format->vsub;
> > > - int aux_x = plane_state->color_plane[1].x;
> > > - int aux_y = plane_state->color_plane[1].y;
> > > - u32 aux_offset = plane_state->color_plane[1].offset;
> > > - u32 alignment = intel_surf_alignment(fb, 1);
> > > + int ccs_plane = main_to_ccs_plane(fb, 0);
> > > + int aux_x = plane_state->color_plane[ccs_plane].x;
> > > + int aux_y = plane_state->color_plane[ccs_plane].y;
> > > + u32 aux_offset = plane_state->color_plane[ccs_plane].offset;
> > > + u32 alignment = intel_surf_alignment(fb, ccs_plane);
> > >
> > > while (aux_offset >= main_offset && aux_y <= main_y) {
> > > int x, y;
> > > @@ -3473,7 +3508,7 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> > >
> > > x = aux_x / hsub;
> > > y = aux_y / vsub;
> > > - aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
> > > + aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, ccs_plane,
> > > aux_offset, aux_offset - alignment);
> > > aux_x = x * hsub + aux_x % hsub;
> > > aux_y = y * vsub + aux_y % vsub;
> > > @@ -3482,9 +3517,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> > > if (aux_x != main_x || aux_y != main_y)
> > > return false;
> > >
> > > - plane_state->color_plane[1].offset = aux_offset;
> > > - plane_state->color_plane[1].x = aux_x;
> > > - plane_state->color_plane[1].y = aux_y;
> > > + plane_state->color_plane[ccs_plane].offset = aux_offset;
> > > + plane_state->color_plane[ccs_plane].x = aux_x;
> > > + plane_state->color_plane[ccs_plane].y = aux_y;
> > >
> > > return true;
> > > }
> > > @@ -3500,7 +3535,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > > int h = drm_rect_height(&plane_state->uapi.src) >> 16;
> > > int max_width;
> > > int max_height;
> > > - u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> > > + int aux_plane = intel_main_to_aux_plane(fb, 0);
> > > + u32 alignment, offset, aux_offset = plane_state->color_plane[aux_plane].offset;
> > >
> > > if (INTEL_GEN(dev_priv) >= 11)
> > > max_width = icl_max_plane_width(fb, 0, rotation);
> > > @@ -3566,7 +3602,8 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
> > > offset, offset - alignment);
> > > }
> > >
> > > - if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
> > > + if (x != plane_state->color_plane[aux_plane].x ||
> > > + y != plane_state->color_plane[aux_plane].y) {
> > > DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
> > > return -EINVAL;
> > > }
> > > --
> > > 2.22.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > VTT-OSGC Platform Enablement
> > Intel Corporation
> > (916) 356-2795
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-12-20 14:03 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-18 16:10 [Intel-gfx] [PATCH 00/15] drm/i915/tgl: Render/media decompression support Imre Deak
2019-12-18 16:10 ` [Intel-gfx] [PATCH 01/15] drm/framebuffer: Format modifier for Intel Gen-12 render compression Imre Deak
2019-12-19 9:01 ` Kahola, Mika
2019-12-19 21:03 ` Matt Roper
2019-12-19 23:30 ` Imre Deak
2019-12-20 10:49 ` Imre Deak
2019-12-20 10:49 ` [Intel-gfx] " Imre Deak
2019-12-18 16:10 ` [Intel-gfx] [PATCH 02/15] drm/i915: Use intel_tile_height() instead of re-implementing Imre Deak
2019-12-19 9:39 ` Kahola, Mika
2019-12-19 21:04 ` Matt Roper
2019-12-18 16:10 ` [Intel-gfx] [PATCH 03/15] drm/i915: Move CCS stride alignment W/A inside intel_fb_stride_alignment Imre Deak
2019-12-19 9:42 ` Kahola, Mika
2019-12-19 21:04 ` Matt Roper
2019-12-18 16:10 ` [Intel-gfx] [PATCH 04/15] drm/i915: Extract framebufer CCS offset checks into a function Imre Deak
2019-12-19 11:10 ` Kahola, Mika
2019-12-19 12:02 ` Imre Deak
2019-12-20 10:49 ` [Intel-gfx] [PATCH v2 " Imre Deak
2019-12-23 7:43 ` Kahola, Mika
2019-12-18 16:10 ` [Intel-gfx] [PATCH 05/15] drm/i915: Add helpers to select correct ccs/aux planes Imre Deak
2019-12-19 11:56 ` Kahola, Mika
2019-12-19 21:04 ` Matt Roper
2019-12-20 0:26 ` Imre Deak
2019-12-20 14:03 ` Ville Syrjälä [this message]
2019-12-20 14:23 ` Imre Deak
2019-12-18 16:10 ` [Intel-gfx] [PATCH 06/15] drm/i915/tgl: Gen-12 render decompression Imre Deak
2019-12-18 17:07 ` [Intel-gfx] [PATCH v2 " Imre Deak
2019-12-19 22:37 ` Sripada, Radhakrishna
2019-12-20 10:49 ` [Intel-gfx] [PATCH v3 " Imre Deak
2019-12-19 19:44 ` [Intel-gfx] [PATCH " Sripada, Radhakrishna
2019-12-18 16:10 ` [Intel-gfx] [PATCH 07/15] drm/i915/tgl: Make sure FBs have a correct CCS plane stride Imre Deak
2019-12-19 12:47 ` Kahola, Mika
2019-12-19 22:48 ` Matt Roper
2019-12-20 0:06 ` Imre Deak
2019-12-18 16:10 ` [Intel-gfx] [PATCH 08/15] drm/i915: Skip rotated offset adjustment for unsupported modifiers Imre Deak
2019-12-18 23:34 ` [Intel-gfx] [PATCH v2 " Imre Deak
2019-12-19 13:31 ` Kahola, Mika
2019-12-18 16:10 ` [Intel-gfx] [PATCH 09/15] drm/i915: Make sure Y slave planes get all the required state Imre Deak
2019-12-19 13:34 ` Kahola, Mika
2019-12-18 16:11 ` [Intel-gfx] [PATCH 10/15] drm/i915: Make sure CCS YUV semiplanar format checks work Imre Deak
2019-12-19 14:14 ` Kahola, Mika
2019-12-19 14:34 ` Imre Deak
2019-12-18 16:11 ` [Intel-gfx] [PATCH 11/15] drm/framebuffer: Format modifier for Intel Gen-12 media compression Imre Deak
2019-12-19 14:17 ` Kahola, Mika
2019-12-20 10:49 ` Imre Deak
2019-12-20 10:49 ` [Intel-gfx] " Imre Deak
2019-12-18 16:11 ` [Intel-gfx] [PATCH 12/15] drm/fb: Extend format_info member arrays to handle four planes Imre Deak
2019-12-19 14:20 ` Kahola, Mika
2019-12-20 10:49 ` Imre Deak
2019-12-20 10:49 ` [Intel-gfx] " Imre Deak
2019-12-18 16:11 ` [Intel-gfx] [PATCH 13/15] drm/i915/tgl: Gen-12 display can decompress surfaces compressed by the media engine Imre Deak
2019-12-19 21:44 ` Sripada, Radhakrishna
2019-12-20 10:49 ` [Intel-gfx] [PATCH v2 " Imre Deak
2019-12-18 16:11 ` [Intel-gfx] [PATCH 14/15] drm/framebuffer: Format modifier for Intel Gen 12 render compression with Clear Color Imre Deak
2019-12-19 14:28 ` Kahola, Mika
2019-12-20 10:49 ` Imre Deak
2019-12-20 10:49 ` [Intel-gfx] " Imre Deak
2019-12-18 16:11 ` [Intel-gfx] [PATCH 15/15] drm/i915/tgl: Add Clear Color support for TGL Render Decompression Imre Deak
2019-12-20 22:58 ` Matt Roper
2019-12-21 16:48 ` Imre Deak
2019-12-18 20:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Render/media decompression support (rev2) Patchwork
2019-12-18 20:54 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2019-12-19 1:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Render/media decompression support (rev3) Patchwork
2019-12-19 1:51 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2019-12-20 10:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Render/media decompression support (rev10) Patchwork
2019-12-20 11:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2019-12-20 13:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Render/media decompression support (rev3) Patchwork
2019-12-20 15:31 ` Imre Deak
2019-12-21 11:50 ` Vudum, Lakshminarayana
2019-12-20 17:07 ` Patchwork
2019-12-21 13:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Render/media decompression support (rev10) Patchwork
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